Changeset 3435


Ignore:
Timestamp:
Nov 15, 2012, 11:24:46 PM (18 months ago)
Author:
wmb
Message:

OLPC ARM - Fixed a build problem by changing the way that the recently introduced clock-divider-regval property is calculated.

Location:
cpu/arm/olpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpu/arm/olpc/1.75/lcdcfg.fth

    r3432 r3435  
    3333   h# 2000000d " lcd-dumb-ctrl-regval" integer-property 
    3434   h# 08001100 " lcd-pn-ctrl0-regval"  integer-property 
    35    clkdiv      " clock-divider-regval" integer-property  \ Depends on MMP2 vs MMP3 
     35 
     36\ In MMP3, the SCLK_SOURCE_SELECT field moved from bit 30 to bit 29, 
     37\ so the high nibble changed from 4 (MMP2) to 2 (MMP3) for the same 
     38\ field value 1. 
     39[ifdef] mmp3  h# 20001102  [else]  h# 40001102  [then]  " clock-divider-regval" integer-property 
    3640 
    3741finish-device 
  • cpu/arm/olpc/lcd.fth

    r3403 r3435  
    1212   d# 41 " interrupts" integer-property 
    1313 
    14 [ifdef] olpc-cl4 
    15 \ This value has the same effect as the value below.  The 
    16 \ difference is that the SCLK_SOURCE_SELECT field added a 
    17 \ low-order bit (bit 29), so the high nibble changed from 
    18 \ 2 to 4 even though the field value is still 1. 
    19 h# 20001102 value clkdiv  \ Display Clock 1 / 2 -> 56.93 MHz 
    20 [else] 
    21 h# 40001102 value clkdiv  \ Display Clock 1 / 2 -> 56.93 MHz 
    22 [then] 
     14\ In MMP3, the SCLK_SOURCE_SELECT field moved from bit 30 to bit 29, 
     15\ so the high nibble changed from 4 (MMP2) to 2 (MMP3) for the same 
     16\ field value 1. 
     17[ifdef] mmp3  h# 20001102  [else]  h# 40001102  [then]  value clkdiv  \ Display Clock 1 / 2 -> 56.93 MHz 
     18 
    2319h# 00000700 value pmua-disp-clk-sel  \ PLL1 / 7 -> 113.86 MHz  
    2420 
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