Changeset 3435

Timestamp:

Nov 15, 2012 11:24:46 PM (6 months ago)

Author:

wmb

Message:

OLPC ARM - Fixed a build problem by changing the way that the recently introduced clock-divider-regval property is calculated.

Location:

cpu/arm/olpc

Files:

• 1.75/lcdcfg.fth (modified) (1 diff)
• lcd.fth (modified) (1 diff)

cpu/arm/olpc/1.75/lcdcfg.fth

@@ -33 +33 @@
    h# 2000000d " lcd-dumb-ctrl-regval" integer-property
    h# 08001100 " lcd-pn-ctrl0-regval"  integer-property
-   clkdiv      " clock-divider-regval" integer-property  \ Depends on MMP2 vs MMP3
+
+\ In MMP3, the SCLK_SOURCE_SELECT field moved from bit 30 to bit 29,
+\ so the high nibble changed from 4 (MMP2) to 2 (MMP3) for the same
+\ field value 1.
+[ifdef] mmp3  h# 20001102  [else]  h# 40001102  [then]  " clock-divider-regval" integer-property
 
 finish-device

cpu/arm/olpc/lcd.fth

@@ -12 +12 @@
    d# 41 " interrupts" integer-property
 
-[ifdef] olpc-cl4
-\ This value has the same effect as the value below.  The
-\ difference is that the SCLK_SOURCE_SELECT field added a
-\ low-order bit (bit 29), so the high nibble changed from
-\ 2 to 4 even though the field value is still 1.
-h# 20001102 value clkdiv  \ Display Clock 1 / 2 -> 56.93 MHz
-[else]
-h# 40001102 value clkdiv  \ Display Clock 1 / 2 -> 56.93 MHz
-[then]
+\ In MMP3, the SCLK_SOURCE_SELECT field moved from bit 30 to bit 29,
+\ so the high nibble changed from 4 (MMP2) to 2 (MMP3) for the same
+\ field value 1.
+[ifdef] mmp3  h# 20001102  [else]  h# 40001102  [then]  value clkdiv  \ Display Clock 1 / 2 -> 56.93 MHz
+
 h# 00000700 value pmua-disp-clk-sel  \ PLL1 / 7 -> 113.86 MHz