Changeset 3335
- Timestamp:
- Sep 27, 2012 2:49:12 AM (9 months ago)
- File:
-
- 1 edited
-
cpu/arm/scc.fth (modified) (1 diff)
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cpu/arm/scc.fth
r2685 r3335 67 67 code clean&flush-l2$-pa ( pa -- ) mcr p15,1,tos,cr7,cr15,3 pop tos,sp c; 68 68 69 \ L2 Cache Extra Features Register 69 70 \ Bit 24 is L2 prefetch disable, bit 23 is L2 ECC enable 70 code l2$-efr ( n -- ) mcr p15,1,tos,cr15,cr1,0 pop tos,sp c; 71 \ Bit 8 (undocumented) enables write-coalescing 72 code l2$-efr! ( n -- ) mcr p15,1,tos,cr15,cr1,0 pop tos,sp c; 73 code l2$-efr@ ( -- n ) psh tos,sp mrc p15,1,tos,cr15,cr1,0 c; 71 74 72 75 code l2$-lockdown-way ( bits -- ) mcr p15,1,tos,cr15,cr10,7 pop tos,sp c;
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