Changeset 3206


Ignore:
Timestamp:
Aug 20, 2012, 11:53:06 PM (3 years ago)
Author:
wmb
Message:

SDHCI - handle host controllers that spuriously set the transfer interrupt bit during cmd13.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • dev/mmc/sdhci/sdhci.fth

    r3164 r3206  
    9393\ unless the interrupt enables are on.
    94940 instance value intstat-count
     95: xfer-int-on  ( -- )  h# 34 cw@  2 or  h# 34 cw!  ;
     96: xfer-int-off ( -- )  h# 34 cw@  2 invert and  h# 34 cw!  ;
     97
    9598: intstat-on  ( -- )
    9699   intstat-count 0=  if
    97       h# 00cb h# 34 cw!  \ normal interrupt status en reg
    98       \ Enable: Remove, Insert, DMA Interrupt, Transfer Complete, CMD Complete
     100      \ Enable: Remove, Insert, DMA Interrupt, CMD Complete
     101      \ Transfer complete is handled separately because some host controllers
     102      \ (e.g. Marvell MMP3) set it spuriously during commands that shouldn't set it.
     103      h# 00c9 h# 34 cw!  \ normal interrupt status en reg
     104
    99105      \ Disable: Card Interrupt, Read Ready, Write Ready, Block Gap
    100106      h# f1ff h# 36 cw!  \ error interrupt status en reg
     
    219225   dup to dma-padr                   ( padr )        \ Remember for later
    220226   0 cl!                                             \ Set address
     227   xfer-int-on
    221228;
    222229
     
    375382: cmd  ( arg cmd mode -- )
    376383   debug?  if  ." CMD: " over 4 u.r space   then
     384
     385   \ R1B-class commands have an implied data transfer phase
     386   over h# ff and  h# 1b  =  if  xfer-int-on  then
     387
    377388   over add-cmd
    378389   wait-ready
     
    452463   h# 061b 0 cmd  response  h# 80 and  if  ." MMC SWITCH_ERROR" cr  then
    453464   2 wait  \ This command appears to have a transfer-complete
     465   xfer-int-off
    454466;
    455467
     
    462474   d# 16 ms   \ Give the operation time to complete
    463475   isr@ isr!
     476   xfer-int-off
    464477;
    465478
     
    10641077;
    10651078
    1066 : wait-dat  ( -- )  d# 10 ms  begin  2 ms present-state@  4 and  0= until  ;
    1067 
    10681079\ Wait for completion
    10691080: r/w-blocks-end  ( in? -- error? )
    10701081   drop
    1071    wait-dat
    10721082   wait-dma-done
    10731083   intstat-on  wait-write-done  intstat-off
     
    10811091: r/w-blocks-start  ( addr block# #blocks in? fresh? -- error? )
    10821092   wait-dma-done    ( addr block# #blocks fresh? in? )
     1093
     1094   \ wait-write-done used to be after dma-setup in an attempt to overlap
     1095   \ work with waiting time, but that doesn't work now that dma-setup
     1096   \ enables transfer interrupts, which can happen spuriously during
     1097   \ wait-write-done on some host controllers.
     1098   wait-write-done  if  3drop  2drop true exit  then  ( addr block# #blocks fresh? in? )
     1099
    10831100   2 pick 0=  if  3drop 2drop  false  exit   then  \ Prevents hangs
    10841101   intstat-on       ( addr block# #blocks fresh? in? )
    10851102   2 pick >r >r >r  ( addr block# #blocks r: #blocks fresh? in? )
    10861103   rot dma-setup    ( block#              r: #blocks fresh? in? )
    1087    wait-write-done  if  drop  r> r> r> 3drop true exit  then  ( block# )
     1104
    10881105   address-shift lshift  r>  if         ( block# r: #blocks fresh? )
    10891106      r> drop                           ( block# r: #blocks )
     
    10981115;
    10991116: fresh-write-blocks-start  ( addr block# #blocks -- error? )
    1100    intstat-on
    1101    wait-dat
    11021117   false true r/w-blocks-start
    11031118;
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