Changeset 3178


Ignore:
Timestamp:
Aug 16, 2012, 12:25:33 AM (3 years ago)
Author:
wmb
Message:

OLPC ARM - Deleted dead code from bbedi.fth

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpu/arm/olpc/bbedi.fth

    r3094 r3178  
    88: edi-clk-hi  ( -- )  ec-edi-clk-gpio# gpio-set  ;
    99
    10 0 [if]
    11 \ All this timing stuff is pointless because the GPIOs are so slow
    12 \ that the problem is to make the clock go fast enough to satisfy
    13 \ the initial connection speed requirement.
    14 
    15 \ We need to run at between 1 and 2 MHz for the initial connection,
    16 \ and then we can go faster, up to 16 Mhz.
    17 \ The half-cycle period for 1-2 MHz is between 250 ns and 500 ns.
    18 \ Timer0 runs at 6.5 MHz so each tick is about 150 ns.
    19 \ Two ticks is 300 ns, three is 450 ns.
    20 code spins  ( count -- )
    21    cmp     tos,#0
    22    <>  if
    23       begin
    24          subs    tos,tos,#1
    25       0= until
    26    then
    27    pop     tos,sp
    28 c;
    29 
    30 d# 150 value edi-dly-spins
    31 : edi-dly  ( -- )  edi-dly-spins spins  ;
    32 
    33 \ CPU clock is 800 Mhz, so 1.25 ns/clock
    34 \ spins is 2 clocks/spin, so 2.5 ns/spin
    35 \ Slow clock must be between 1 and 2 MHz, so period is between 1000 and 500 ns.
    36 \ edi-dly is a half cycle, so edi-dly for slow clock is between 500 and 250 ns.
    37 \ So we need between 200 and 100 spins for slow edi-dly
    38 \ Fast clock can be up to 16 Mhz, so full-cycle period of 62.5 ns, half-cycle
    39 \ period of >= 31.25 ns, so >= 12.5 spins at 2.5. ns/spin.
    40 
    41 : slow-edi-clock  ( -- )  d# 150 to edi-dly-spins  ;
    42 : fast-edi-clock  ( -- )  d# 13 to edi-dly-spins  ;
    43 
    44 code edi-bit!  ( flag -- )
    45    mov   r0,#0x200
    46    set   r1,`h# 19100 +io #`
    47    cmp   tos,#0
    48    streq r0,[r1,#0x24]  \ Clr MOSI if flag is 0
    49    strne r0,[r1,#0x18]  \ Set MOSI if flag is non0
    50    mov   r0,#0x400
    51    str   r0,[r1,#0x18]  \ Set CLK
    52    str   r0,[r1,#0x24]  \ Clr CLK
    53    pop tos,sp
    54 c;
    55 
    56 [ifndef] edi-bit!
    57 : edi-bit!  ( flag -- )
    58    ec-edi-mosi-gpio#  swap  if  gpio-set  else  gpio-clr  then
    59    edi-clk-hi
    60    edi-dly
    61    edi-clk-lo
    62    edi-dly
    63 ;
    64 [then]
    65 
    66 [ifndef] edi-bit!
    67 : edi-bit!  ( flag -- )
    68    if
    69       [ ec-edi-mosi-gpio# >gpio-pin h# 18 + ] dliteral io!  \ Fast gpio-set
    70    else
    71       [ ec-edi-mosi-gpio# >gpio-pin h# 24 + ] dliteral io!  \ Fast gpio-clr
    72    then
    73    [ ec-edi-clk-gpio# >gpio-pin h# 18 + ] dliteral io!  \ Fast gpio-set
    74 \   edi-dly
    75    [ ec-edi-clk-gpio# >gpio-pin h# 24 + ] dliteral io!  \ Fast gpio-set
    76 \   edi-dly
    77 ;
    78 [then]
    79 
    80 : edi-out  ( b -- )
    81    8 0  do                   ( b )
    82       dup h# 80 and edi-bit! ( b )
    83       2*                     ( b' )
    84    loop                      ( b )
    85    drop                      ( )
    86 ;   
    87 : edi-bit@  ( -- flag )
    88    edi-clk-hi
    89    edi-dly
    90    ec-edi-miso-gpio# gpio-pin@
    91    edi-clk-lo
    92    edi-dly
    93 ;
    94 : edi-in-h  ( b -- )
    95    0                         ( b )
    96    8 0  do                   ( b )
    97       2* edi-bit@ 1 and or   ( b' )
    98    loop                      ( b )
    99 ;   
    100 [else]
     10\ This must be done in code to satisfy the stringent timing requirements of the EDI hardware
    10111code edi-out  ( byte -- )
    10212   mov   r2,#8
     
    11828
    11929      str   r4,[r1,#0x18]  \ Set CLK
    120       str   r4,[r1,#0x24]  \ Clr CLK
    121 
    122       add   tos,tos,tos    \ Left shift TOS     
    123    decs r2,1
    124    0= until
    125 
    126    pop tos,sp
    127 c;
    128 code edi-out1  ( byte -- )
    129    mov   r2,#8
    130    mov   r0,#0x200           \ MOSI mask
    131    set   r1,`h# 19100 +io #` \ GPIO register address
    132    mov   r4,#0x400           \ CLK mask
    133    mov   r5,#0x600           \ CLK and MOSI mask
    134    begin
    135       ands  r3,tos,#0x80   \ Test bit
    136 
    137       strne r5,[r1,#0x18]  \ Set MOSI and CLK in the same operation if bit is non0
    138       streq r0,[r1,#0x24]  \ Clr MOSI
    139       streq r4,[r1,#0x18]  \ Set CLK
    140 
    14130      str   r4,[r1,#0x24]  \ Clr CLK
    14231
     
    18170c;
    18271
    183 [then]
    184 
    185 
    18672: edi-spi-start  ( -- )
    18773   ['] edi-in      to spi-in
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