Changeset 3163


Ignore:
Timestamp:
Aug 13, 2012, 10:41:29 PM (20 months ago)
Author:
wmb
Message:

SDHCI driver - Wait for write operations to complete more aggressively than before. This fixes a fs-update problem with XO-4. I'm not entirely convinced that this is the right fix, so it probably needs more study, but for now, it seems to work.

File:
1 edited

Legend:

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  • dev/mmc/sdhci/sdhci.fth

    r3111 r3163  
    451451: mmc-switch  ( arg -- )    \ CMD6 for MMC - no data 
    452452   h# 061b 0 cmd  response  h# 80 and  if  ." MMC SWITCH_ERROR" cr  then 
     453   2 wait  \ This command appears to have a transfer-complete 
    453454; 
    454455 
     
    459460   \ Specification says that Transfer Complete is set after R1b 
    460461   \ commands, so we must clear that bit if it is set. 
     462   d# 16 ms   \ Give the operation time to complete 
    461463   isr@ isr! 
    462464; 
     
    761763      \ Ideally, the width selection would be done by using CMD19 to test the bus 
    762764      hc-supports-8-bit?  if 
    763          mmc-8-bit  1 ms  8-bit 
     765         mmc-8-bit  8-bit 
    764766      else 
    765          mmc-4-bit  1 ms  4-bit 
     767         mmc-4-bit  4-bit 
    766768      then 
    767769 
     
    10621064; 
    10631065 
     1066: wait-dat  ( -- )  d# 10 ms  begin  2 ms present-state@  4 and  0= until  ; 
     1067 
    10641068\ Wait for completion 
    10651069: r/w-blocks-end  ( in? -- error? ) 
    10661070   drop 
     1071   wait-dat 
    10671072   wait-dma-done 
    10681073   intstat-on  wait-write-done  intstat-off 
     
    10931098; 
    10941099: fresh-write-blocks-start  ( addr block# #blocks -- error? ) 
     1100   intstat-on 
     1101   wait-dat 
    10951102   false true r/w-blocks-start 
    10961103; 
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