Changeset 2993


Ignore:
Timestamp:
May 31, 2012, 10:07:15 PM (3 years ago)
Author:
wmb
Message:

OLPC XO-1.75 - Added support for 910 MHz and 1 GHz (actually 988 MHz) operating points.

Location:
cpu/arm
Files:
1 added
3 edited

Legend:

Unmodified
Added
Removed
  • cpu/arm/mmp2/clocks.fth

    r2390 r2993  
    11purpose: Change the clock frequency
     2
     30 [if]
     4: set-pll2-520mhz  ( -- )
     5   \ select PLL2 frequency, 520MHz
     6   h# 08600322 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6)
     7   h# 00FFFE00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation
     8   h# 0021da00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor=4, feedback divisor=0x76=118, software controls activation
     9   h# 0021db00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ same plus enable
     10   h# 28600322 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter
     11;
     12[then]
     13: set-pll2-910mhz  ( -- )
     14   \ select PLL2 frequency, 910MHz
     15   h# 086005a2 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6)
     16   h# 00FFFE00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation
     17   h# 00234200 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor=4, feedback divisor=0xd0=208, software controls activation
     18   h# 00234300 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ same plus enable
     19   h# 286005a2 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter
     20;
     21: set-pll2-988mhz  ( -- )
     22   \ select PLL2 frequency, 988MHz
     23   h# 08600622 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 971.35-1011.65 PLL2 (bits 10:6)
     24   h# 00FFFE00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation
     25   h# 00238a00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor=4, feedback divisor=0xe2=226, software controls activation
     26   h# 00238b00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ same plus enable
     27   h# 28600622 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter
     28;
     29: pll2-off  ( -- )
     30   h# 2000.0000 h#  414 +mpmu io-clr  \ PLL2_RESETB in PMUM_PLL2_CTRL1
     31   h#       100 h#   34 +mpmu io-clr  \ PLL2_SW_EN in PMUM_PLL2CR
     32;
     33: gate-pll2  ( -- )
     34   h#      4000 h# 1024 +mpmu io-clr  \ APMU_PLL2 in PMUM_CGR_PJ
     35   h#      4000 h#   24 +mpmu io-clr  \ APMU_PLL2 in PMUM_CGR_SP
     36;
     37: ungate-pll2  ( -- )
     38   h#      4000 h# 1024 +mpmu io-set  \ APMU_PLL2 in PMUM_CGR_PJ
     39   h#      4000 h#   24 +mpmu io-set  \ APMU_PLL2 in PMUM_CGR_SP
     40;
    241
    342: fccr@    ( -- n )  h# 05.0008 io@  ;
     
    2665: pj4-400mhz ( -- )  0 pj4-clksel  o# 37042301100 pj4-cc!  ;  \ A 200, D 400, XP 200, B 200, P 400
    2766: pj4-800mhz ( -- )  1 pj4-clksel  o# 37042201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 800
     67: pj4-910mhz ( -- )  set-pll2-910mhz ungate-pll2  2 pj4-clksel  o# 37042201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 910
     68: pj4-988mhz ( -- )  set-pll2-988mhz ungate-pll2  2 pj4-clksel  o# 37042201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 910
     69: .speed  ( -- )  t( d# 10,000,000 0 do loop )t   ;
    2870
    29710 [if]
     
    3375: pj4-400mhz ( -- )  0 pj4-clksel  o# 21742301100 pj4-cc!  ;  \ A 200, D 400, XP 200, B 200, P 400
    3476: pj4-800mhz ( -- )  1 pj4-clksel  o# 21742201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 800
     77: pj4-910mhz ( -- )  set-pll2-910mhz 2 pj4-clksel  o# 21742201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 910
     78: pj4-988mhz ( -- )  set-pll2-988mhz 2 pj4-clksel  o# 21742201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 988
    3579[then]
  • cpu/arm/mmp2/fuse.fth

    r2576 r2993  
    3737: .3bits  ( n -- n' )  dup 7 and .d  3 rshift  ;
    3838string-array freqs  ," 800" ," 910" ," 1001" ," ??? " end-string-array
    39 : .max-freq  ( n -- ) ."  Max Freq: " 3 and freqs count type   ;
     39: rated-speed  ( -- n )  h# 28a4 fuse@  d# 14 rshift 3 and  ;
     40: .max-freq  ( -- ) ."  Max Freq: " rated-speed freqs count type   ;
    4041: .block3-brief  ( -- )
    4142   ." Block 3 - Voltages: "  h# 28a0 fuse@  5 0 do  .3bits  loop  2/  .3bits drop
    42    h# 28a4 fuse@  d# 14 rshift .max-freq  cr
     43   .max-freq  cr
    4344;
    4445: .block3  ( -- )
  • cpu/arm/olpc/build-fw.fth

    r2987 r2993  
    568568;
    569569
    570 fload ${BP}/cpu/x86/pc/olpc/via/banner.fth
     570fload ${BP}/cpu/arm/olpc/banner.fth
    571571
    572572\- olpc-cl3  devalias keyboard /ap-sp/keyboard
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