Changeset 2993

Timestamp:

May 31, 2012 10:07:15 PM (13 months ago)

Author:

wmb

Message:

OLPC XO-1.75 - Added support for 910 MHz and 1 GHz (actually 988 MHz) operating points.

Location:

cpu/arm

Files:

• mmp2/clocks.fth (modified) (3 diffs)
• mmp2/fuse.fth (modified) (1 diff)
• olpc/banner.fth (added)
• olpc/build-fw.fth (modified) (1 diff)

cpu/arm/mmp2/clocks.fth

@@ -1 +1 @@
 purpose: Change the clock frequency
+
+0 [if]
+: set-pll2-520mhz  ( -- )
+   \ select PLL2 frequency, 520MHz
+   h# 08600322 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6)
+   h# 00FFFE00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation
+   h# 0021da00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor=4, feedback divisor=0x76=118, software controls activation
+   h# 0021db00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ same plus enable
+   h# 28600322 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter
+;
+[then]
+: set-pll2-910mhz  ( -- )
+   \ select PLL2 frequency, 910MHz
+   h# 086005a2 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6)
+   h# 00FFFE00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation
+   h# 00234200 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor=4, feedback divisor=0xd0=208, software controls activation
+   h# 00234300 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ same plus enable
+   h# 286005a2 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter
+;
+: set-pll2-988mhz  ( -- )
+   \ select PLL2 frequency, 988MHz
+   h# 08600622 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 971.35-1011.65 PLL2 (bits 10:6)
+   h# 00FFFE00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation
+   h# 00238a00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ refclk divisor=4, feedback divisor=0xe2=226, software controls activation
+   h# 00238b00 h#  34 mpmu!  \ PMUM_PLL2_CTRL2 \ same plus enable
+   h# 28600622 h# 414 mpmu!  \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter
+;
+: pll2-off  ( -- )
+   h# 2000.0000 h#  414 +mpmu io-clr  \ PLL2_RESETB in PMUM_PLL2_CTRL1
+   h#       100 h#   34 +mpmu io-clr  \ PLL2_SW_EN in PMUM_PLL2CR
+;
+: gate-pll2  ( -- )
+   h#      4000 h# 1024 +mpmu io-clr  \ APMU_PLL2 in PMUM_CGR_PJ
+   h#      4000 h#   24 +mpmu io-clr  \ APMU_PLL2 in PMUM_CGR_SP
+;
+: ungate-pll2  ( -- )
+   h#      4000 h# 1024 +mpmu io-set  \ APMU_PLL2 in PMUM_CGR_PJ
+   h#      4000 h#   24 +mpmu io-set  \ APMU_PLL2 in PMUM_CGR_SP
+;
 
 : fccr@    ( -- n )  h# 05.0008 io@  ;
@@ -26 +65 @@
 : pj4-400mhz ( -- )  0 pj4-clksel  o# 37042301100 pj4-cc!  ;  \ A 200, D 400, XP 200, B 200, P 400
 : pj4-800mhz ( -- )  1 pj4-clksel  o# 37042201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 800
+: pj4-910mhz ( -- )  set-pll2-910mhz ungate-pll2  2 pj4-clksel  o# 37042201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 910
+: pj4-988mhz ( -- )  set-pll2-988mhz ungate-pll2  2 pj4-clksel  o# 37042201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 910
+: .speed  ( -- )  t( d# 10,000,000 0 do loop )t   ;
 
 0 [if]
@@ -33 +75 @@
 : pj4-400mhz ( -- )  0 pj4-clksel  o# 21742301100 pj4-cc!  ;  \ A 200, D 400, XP 200, B 200, P 400
 : pj4-800mhz ( -- )  1 pj4-clksel  o# 21742201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 800
+: pj4-910mhz ( -- )  set-pll2-910mhz 2 pj4-clksel  o# 21742201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 910
+: pj4-988mhz ( -- )  set-pll2-988mhz 2 pj4-clksel  o# 21742201100 pj4-cc!  ;  \ A 266, D 400, XP 400, B 400, P 988
 [then]

cpu/arm/mmp2/fuse.fth

@@ -37 +37 @@
 : .3bits  ( n -- n' )  dup 7 and .d  3 rshift  ;
 string-array freqs  ," 800" ," 910" ," 1001" ," ??? " end-string-array
-: .max-freq  ( n -- ) ."  Max Freq: " 3 and freqs count type   ;
+: rated-speed  ( -- n )  h# 28a4 fuse@  d# 14 rshift 3 and  ;
+: .max-freq  ( -- ) ."  Max Freq: " rated-speed freqs count type   ;
 : .block3-brief  ( -- )
    ." Block 3 - Voltages: "  h# 28a0 fuse@  5 0 do  .3bits  loop  2/  .3bits drop
-   h# 28a4 fuse@  d# 14 rshift .max-freq  cr
+   .max-freq  cr
 ;
 : .block3  ( -- )

cpu/arm/olpc/build-fw.fth

@@ -568 +568 @@
 ;
 
-fload ${BP}/cpu/x86/pc/olpc/via/banner.fth
+fload ${BP}/cpu/arm/olpc/banner.fth
 
 \- olpc-cl3  devalias keyboard /ap-sp/keyboard