Changeset 2942


Ignore:
Timestamp:
Apr 12, 2012, 11:28:34 PM (3 years ago)
Author:
wmb
Message:

OLPC XO-1.75 and XO-3 - changed EDI (SPI interface to EC) timing to account for rise time issue on MISO.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpu/arm/olpc/bbedi.fth

    r2726 r2942  
    104104;   
    105105[else]
    106 code edi-out0  ( byte -- )
     106code edi-out  ( byte -- )
    107107   mov   r2,#8
    108108   mov   r0,#0x200           \ MOSI mask
     
    113113
    114114      strne r0,[r1,#0x18]  \ Set MOSI if bit is non0
     115      strne r0,[r1,#0x18]  \ Set MOSI if bit is non0  \ Twice for delay - setup time to CLK
    115116      streq r0,[r1,#0x24]  \ Clr MOSI if bit is 0
     117      streq r0,[r1,#0x24]  \ Clr MOSI if bit is 0  \ Twice for delay - setup time to CLK
    116118
    117119      str   r4,[r1,#0x18]  \ Set CLK
     
    124126   pop tos,sp
    125127c;
    126 code edi-out  ( byte -- )
     128code edi-out1  ( byte -- )
    127129   mov   r2,#8
    128130   mov   r0,#0x200           \ MOSI mask
     
    159161      \ This delay is necessary to let the MMP2 GPIO pin clock in the
    160162      \ data value.  Without the delay, bit values get lost.
    161       mov   r7,#0x160      \ Delay spins
     163      mov   r7,#0x400      \ Delay spins
    162164      begin
    163165         decs r7,#1
     
    167169      str   r0,[r3],#4
    168170      str   r4,[r1,#0x24]  \ Clr CLK
     171      mov   r7,#0x400      \ Delay spins
     172      begin
     173         decs r7,#1
     174      0= until
     175
    169176      ands  r0,r0,#0x80    \ Test MISO bit
    170177      incne tos,1          \ Set bit in byte
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