Changeset 2678


Ignore:
Timestamp:
Nov 9, 2011, 5:00:22 AM (4 years ago)
Author:
wmb
Message:

OLPC XO-1.75 - fixed high speed TWSI operation based on new information about how the registers work.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpu/arm/mmp2/twsi.fth

    r2664 r2678  
    1616: sar@  ( -- n )  twsi-chip h# 20 + io@   ;
    1717: lcr@  ( -- n )  twsi-chip h# 28 + io@   ;
     18: wcr@  ( -- n )  twsi-chip h# 30 + io@   ;
    1819: dbr!  ( n -- )  twsi-chip h# 08 + io!   ;
    1920: cr!   ( n -- )  twsi-chip h# 10 + io!   ;
     
    2122: sar!  ( n -- )  twsi-chip h# 20 + io!   ;
    2223: lcr!  ( n -- )  twsi-chip h# 28 + io!   ;
     24: wcr!  ( -- n )  twsi-chip h# 30 + io!   ;
    2325
    2426create channel-bases
     
    5961h# 1000 constant BBU_TWSI_TimeOut          \ TWSI bus timeout loop counter value
    6062
     63d#   26 constant ftwsi-mhz  \
     64d# 1400 constant tlow-nsec  \ The I2C spec calls for Tlow >= 1300 ns
     65ftwsi-mhz tlow-nsec d# 1000 */ constant tlow-ticks
     66
    6167bbu_ICR_IUE bbu_ICR_SCLE or value cr-set   \ bits to maintain as set
    6268: init-twsi-channel  ( channel# -- )
     
    6874   0 sar!                        \ Set host slave address
    6975   0 cr!                         \ Disable interrupts
     76   \ The COUNT field of TWSI_WCR establishes a minimum value for the SCL low time.
     77   \ The minimum Tlow is the clock period * (12 + 2*COUNT)
     78   wcr@ h# 1f invert and  tlow-ticks d# 12 - 2/  or  wcr!  \ Setup and hold times
    7079;
    7180: init-twsi  ( -- )
     
    178187;
    179188
    180 : set-bus-standard  cr-set  h# fffe7fff and              to cr-set  ;
    181 : set-bus-fast      cr-set  h# fffe7fff and  h# 8000 or  to cr-set  ;
    182 
    183 \ The dividends below (12,600,000 and 11,600,000) are chosen to give the
    184 \ same values that the LCR defaults to for the data rates 100,000 and 400,000
    185 \ The TWSI input clock is the 26 MHz VCXO, and the divided value generates
    186 \ both the low phase and the high phase, so you would think that the dividend
    187 \ should be 13,000,000 (half of 26M), but that doesn't give the right result.
    188 \ Perhaps there is an additive factor in the divisor; the manual is quite vague.
     189
     190: set-bus-standard  cr-set  h# 18000 invert and              to cr-set  ;
     191: set-bus-fast      cr-set  h# 18000 invert and  h# 8000 or  to cr-set  ;
     192
    189193: set-bus-speed  ( hz -- )  \ Useful range is 25K .. 400K - 100K and 400K are typical
    190194   child-address set-twsi-target                         ( hz )
    191    dup  d# 100,000 <=  if                                ( hz )
    192       set-bus-standard                                   ( hz )
    193       d# 12,600,000  swap /  h# 1ff min  h# 7e max       ( divisor )
     195   ftwsi-mhz d# 1,000,000  2 pick */                     ( hz ticks )
     196   swap  d# 100,000 <=  if                               ( ticks )
     197      \ In slow mode, Thi = Tclk * (8+slv), Tlow = Tclk * (1+slv)
     198      9 -  2/ 1+                                         ( slv )
    194199      lcr@ h# 1ff invert and  or  lcr!                   ( )
    195    else                                                  ( hz )
    196       set-bus-fast                                       ( hz )
    197       d# 11,600,000  swap /  h# 1ff min  h# 1d max       ( divisor )
    198       lcr@ h# 3.fe00 invert and  swap 9 lshift or  lcr!  ( )
     200      set-bus-standard                                   ( )
     201   else                                                  ( ticks )
     202      \ (The information below is poorly documented and was determined empirically)
     203      \ In fast mode, Thi = Tclk * (10+flv), Tlo = Tclk * max(1+flv, tlow_ticks))
     204      dup d# 11 - 2/ 1+  tlow-ticks  max                 ( ticks ticks-low )
     205      -  d# 10 -                                         ( flv )
     206      9 lshift  lcr@ h# 3.fe00 invert and  or  lcr!      ( )
     207      set-bus-fast                                       ( )
    199208   then                                                  ( )
    200209;
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