Changeset 2352
- Timestamp:
- Jul 14, 2011 1:28:41 AM (2 years ago)
- File:
-
- 1 edited
-
cpu/arm/olpc/1.75/xo-dram.fth (modified) (15 diffs)
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cpu/arm/olpc/1.75/xo-dram.fth
r1987 r2352 78 78 mmap0 79 79 h# 0000.0000 d# 23 rshift start-addr 80 h# 4000.0000 log2 d# 16 - area-length80 h# 2000.0000 log2 d# 16 - area-length 81 81 h# 0000.0000 d# 23 rshift addr-mask 82 82 1 cs-valid … … 84 84 85 85 mmap1 86 h# 4000.0000 d# 23 rshift start-addr87 h# 4000.0000 log2 d# 16 - area-length86 h# 2000.0000 d# 23 rshift start-addr 87 h# 2000.0000 log2 d# 16 - area-length 88 88 h# 0000.0000 d# 23 rshift addr-mask 89 0cs-valid89 1 cs-valid 90 90 outbits 91 91 … … 167 167 168 168 sdram-timing4 169 d# 5.625 ns>clk d# 4 maxtcke169 d# 5.625 ns>clk ( d# 4 max ) tcke 170 170 d# 200000.000 ns>clk d# 1024 /roundup init-count 171 1trwd-ext-dly171 2 trwd-ext-dly 172 172 d# 100.000 ns>clk reset-count 173 d# 39 0init-count-nop173 d# 391 init-count-nop 174 174 outbits 175 175 176 176 sdram-timing5 177 177 d# 37.500 ns>clk 0 max tras 178 d# 37.500 ns>clk 0 max tfaw178 d# 37.500 ns>clk d# 20 max tfaw 179 179 d# 1 tccd-ccs-ext-dly 180 180 outbits … … 187 187 188 188 sdram-ctrl1 189 1 aps-en190 1 aps-type191 4 aps-value189 0 aps-en \ 1 aps-en 190 0 aps-type \ 1 aps-type 191 0 aps-value \ 4 aps-value 192 192 d# 12.500 ns>clk acs-exit-dly 193 193 0 acs-en … … 199 199 200 200 sdram-ctrl2 201 0ref-posted-en202 0ref-posted-max203 d# 16sdram-line-boundary201 1 ref-posted-en 202 7 ref-posted-max 203 d# 8 sdram-line-boundary 204 204 0 refpb-mode 205 205 0 pd-mode 206 206 0 2t-mode 207 207 0 rdimm-mode 208 1aprecharge208 0 aprecharge 209 209 0 int-shadow-mode 210 210 0 test-mode … … 236 236 0 al-en 237 237 0 rq-ds-en 238 3cas-latency \ For DDR3, upper 3 bits of CL - so 3 for CL6 and CL7238 2 cas-latency \ For DDR3, upper 3 bits of CL - so 3 for CL6 and CL7 239 239 0 cas-latency-lower \ For DDR3, lower bit of CL - so 0 for CL6, 1 for CL7 240 1cwl \ 0 for WL5, 1 for WL6, 2 for WL7, 3 for WL8240 0 cwl \ 0 for WL5, 1 for WL6, 2 for WL7, 3 for WL8 241 241 0 s4-type \ LPDDR2 only 242 242 0 asr \ DDR3 only … … 268 268 269 269 sdram-ctrl8-odt-ctrl2 270 1xpage-en270 0 xpage-en 271 271 3 mc-queue-size-f 272 272 3 mc-queue-size … … 355 355 outbits 356 356 357 phy-ctrl11 358 0 mc-sync-type 359 outbits 360 361 \ This is the base value 362 phy-ctrl14 363 1 phy-sync-en 364 0 dll-update-en 365 0 phy-dll-rst 366 0 phy-pll-rst 367 0 dll-update-en-static 368 outbits 369 370 \ Assert DLL reset 371 phy-ctrl14 372 1 phy-sync-en 373 0 dll-update-en 374 1 phy-dll-rst 375 0 phy-pll-rst 376 0 dll-update-en-static 377 outbits 378 379 \ Release DLL reset 380 phy-ctrl14 381 1 phy-sync-en 382 0 dll-update-en 383 0 phy-dll-rst 384 0 phy-pll-rst 385 0 dll-update-en-static 386 outbits 387 357 \ phy-ctrl11 358 \ 0 mc-sync-type 359 \ outbits 360 361 0 [if] 388 362 \ First value, with auto-cal enabled 389 363 phy-ctrl10 … … 419 393 0 mc-ac-d 420 394 outbits 395 [then] 421 396 422 397 phy-ctrl3 … … 427 402 0 dq-oen-dly 428 403 0 rd-ext-dly 429 4phy-rfifo-rptr-dly-val \ Tune me !!!430 4dq-ext-dly \ Tune me !!!404 3 phy-rfifo-rptr-dly-val \ Tune me !!! 405 3 dq-ext-dly \ Tune me !!! 431 406 outbits 432 407 433 408 phy-ctrl7 434 409 1 phy-qs-vref-sel 435 b# 1111 phy-dq-zpdrv436 b# 1111 phy-dq-zndrv410 b# 0111 phy-dq-zpdrv 411 b# 0111 phy-dq-zndrv 437 412 b# 1000 phy-dq-zptrm 438 413 b# 0100 phy-dq-zntrm 439 b# 1000phy-dq-znr440 b# 0100phy-dq-zpr414 b# 0111 phy-dq-znr 415 b# 1001 phy-dq-zpr 441 416 b# 10 phy-dq-vref-sel 442 417 0 phy-dq-zd … … 445 420 446 421 phy-ctrl8 447 b# 1111 phy-adcm-zpdrv448 b# 1111 phy-adcm-zndrv422 b# 0111 phy-adcm-zpdrv 423 b# 0111 phy-adcm-zndrv 449 424 b# 0000 phy-adcm-zptrm 450 425 b# 0000 phy-adcm-zntrm 451 b# 1000phy-adcm-znr452 b# 0100phy-adcm-zpr426 b# 0111 phy-adcm-znr 427 b# 1001 phy-adcm-zpr 453 428 0 phy-adcm-zd 454 429 outbits … … 464 439 0 phy-wck-ac-dly 465 440 0 phy-wck-ck-dly 466 b# 1000phy-ck-znr467 b# 01 00phy-ck-zpr441 b# 0111 phy-ck-znr 442 b# 0111 phy-ck-zpr 468 443 outbits 469 444 470 445 phy-ctrl13 471 2dll-resrt-timer446 d# 13 dll-resrt-timer 472 447 0 dll-update-stall-mc-dis 473 d# 16dll-delay-test474 d# 0 8dll-phsel475 1dll-auto-manual-up448 0 dll-delay-test 449 d# 04 dll-phsel 450 0 dll-auto-manual-up 476 451 0 dll-auto-update-en 477 452 0 dll-test-en … … 480 455 481 456 phy-dll-ctrl1 482 d# 16dll-delay-test483 d# 8dll-phsel457 0 dll-delay-test 458 d# 4 dll-phsel 484 459 0 dll-auto-update-en 485 460 0 dll-test-en … … 488 463 489 464 phy-dll-ctrl2 490 d# 16dll-delay-test491 d# 8dll-phsel465 0 dll-delay-test 466 d# 4 dll-phsel 492 467 0 dll-auto-update-en 493 468 0 dll-test-en … … 496 471 497 472 phy-dll-ctrl3 498 d# 16dll-delay-test499 d# 8dll-phsel473 0 dll-delay-test 474 d# 4 dll-phsel 500 475 0 dll-auto-update-en 501 476 0 dll-test-en 502 477 0 dll-bypass-en 478 outbits 479 480 \ Assert DLL reset 481 phy-ctrl14 482 0 phy-sync-en 483 0 dll-update-en 484 1 phy-dll-rst 485 0 phy-pll-rst 486 0 dll-update-en-static 487 outbits 488 489 \ Release DLL reset and enable update 490 phy-ctrl14 491 0 phy-sync-en 492 1 dll-update-en 493 0 phy-dll-rst 494 0 phy-pll-rst 495 0 dll-update-en-static 503 496 outbits 504 497
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