Changeset 1201 for trunk/spi25.c

Timestamp:

Oct 8, 2010 2:37:55 AM (3 years ago)

Author:

hailfinger

Message:

SPI write status register (WRSR) may take longer than 100 ms, and it
makes sense to poll for completion in 10 ms steps until 5 s are over.
This patch complements r1115.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@…>
Acked-by: Joshua Roys <roysjosh@…>

File:

• trunk/spi25.c (modified) (4 diffs)

trunk/spi25.c

@@ -857 +857 @@
 {
         int result;
+        int i = 0;
         struct spi_command cmds[] = {
         {
@@ -880 +881 @@
                 msg_cerr("%s failed during command execution\n",
                         __func__);
-        }
-        /* WRSR performs a self-timed erase before the changes take effect. */
+                /* No point in waiting for the command to complete if execution
+                 * failed.
+                 */
+                return result;
+        }
+        /* WRSR performs a self-timed erase before the changes take effect.
+         * This may take 50-85 ms in most cases, and some chips apparently
+         * allow running RDSR only once. Therefore pick an initial delay of
+         * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
+         */
         programmer_delay(100 * 1000);
-        return result;
+        while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) {
+                if (++i > 490) {
+                        msg_cerr("Error: WIP bit after WRSR never cleared\n");
+                        return TIMEOUT_ERROR;
+                }
+                programmer_delay(10 * 1000);
+        }
+        return 0;
 }
 
@@ -889 +905 @@
 {
         int result;
+        int i = 0;
         struct spi_command cmds[] = {
         {
@@ -912 +929 @@
                 msg_cerr("%s failed during command execution\n",
                         __func__);
-        }
-        /* WRSR performs a self-timed erase before the changes take effect. */
+                /* No point in waiting for the command to complete if execution
+                 * failed.
+                 */
+                return result;
+        }
+        /* WRSR performs a self-timed erase before the changes take effect.
+         * This may take 50-85 ms in most cases, and some chips apparently
+         * allow running RDSR only once. Therefore pick an initial delay of
+         * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
+         */
         programmer_delay(100 * 1000);
-        return result;
+        while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) {
+                if (++i > 490) {
+                        msg_cerr("Error: WIP bit after WRSR never cleared\n");
+                        return TIMEOUT_ERROR;
+                }
+                programmer_delay(10 * 1000);
+        }
+        return 0;
 }