AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock

[edwin_beasant@…]

The AMD DB800 board PLL strappings are left open as supplied, and leave the CPU/Memory in the sub-optimal 400MHz CPU,266MHz GLIU configuration.
This requires a manual PLL strapping to achieve 500Mhz CPU and 400MHz GLIU as is normally used in the dev-kits (and the commercial GeodeRom?).
These are the correct (manual) strappings for a DB800:
#define PLLMSRhi 0x000005DD
#define PLLMSRlo 0x00DE60EE
Patch attached.

[stepan]

Please send a Signed-off according to http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure so we can use your code.