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Opened 5 years ago

Last modified 5 years ago

#150 new enhancement

AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock

Reported by: edwin_beasant@… Owned by: somebody
Priority: minor Milestone:
Component: coreboot Keywords:
Cc: Dependencies:
Patch Status: patch needs review

Description

The AMD DB800 board PLL strappings are left open as supplied, and leave the CPU/Memory in the sub-optimal 400MHz CPU,266MHz GLIU configuration. This requires a manual PLL strapping to achieve 500Mhz CPU and 400MHz GLIU as is normally used in the dev-kits (and the commercial GeodeRom?). These are the correct (manual) strappings for a DB800: #define PLLMSRhi 0x000005DD #define PLLMSRlo 0x00DE60EE Patch attached.

Attachments (1)

coreboot-v2-r4791-db800-pll.patch (712 bytes) - added by edwin_beasant@… 5 years ago.

Download all attachments as: .zip

Change History (2)

Changed 5 years ago by edwin_beasant@…

comment:1 Changed 5 years ago by stepan

Please send a Signed-off according to http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure so we can use your code.

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