Changeset 5207
- Timestamp:
- Mar 14, 2010 6:01:08 PM (3 years ago)
- Location:
- trunk/src/southbridge/intel/i82801dx
- Files:
-
- 2 deleted
- 15 edited
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Kconfig (modified) (1 diff)
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Makefile.inc (modified) (1 diff)
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chip.h (modified) (2 diffs)
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cmos_failover.c (modified) (1 diff)
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i82801dx.c (modified) (4 diffs)
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i82801dx.h (modified) (2 diffs)
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i82801dx_early_smbus.c (modified) (11 diffs)
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i82801dx_ide.c (modified) (2 diffs)
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i82801dx_lpc.c (modified) (8 diffs)
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i82801dx_nic.c (deleted)
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i82801dx_pci.c (modified) (2 diffs)
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i82801dx_reset.c (modified) (1 diff)
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i82801dx_sata.c (deleted)
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i82801dx_smbus.c (modified) (6 diffs)
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i82801dx_tco_timer.c (modified) (3 diffs)
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i82801dx_usb.c (modified) (2 diffs)
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i82801dx_usb2.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/southbridge/intel/i82801dx/Kconfig
r5177 r5207 1 ## 2 ## This file is part of the coreboot project. 3 ## 4 ## Copyright (C) 2008-2009 coresystems GmbH 5 ## 6 ## This program is free software; you can redistribute it and/or 7 ## modify it under the terms of the GNU General Public License as 8 ## published by the Free Software Foundation; version 2 of 9 ## the License. 10 ## 11 ## This program is distributed in the hope that it will be useful, 12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of 13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 ## GNU General Public License for more details. 15 ## 16 ## You should have received a copy of the GNU General Public License 17 ## along with this program; if not, write to the Free Software 18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 19 ## MA 02110-1301 USA 20 ## 21 1 22 config SOUTHBRIDGE_INTEL_I82801DX 2 23 bool -
trunk/src/southbridge/intel/i82801dx/Makefile.inc
r5177 r5207 1 ## 2 ## This file is part of the coreboot project. 3 ## 4 ## Copyright (C) 2008-2009 coresystems GmbH 5 ## 6 ## This program is free software; you can redistribute it and/or 7 ## modify it under the terms of the GNU General Public License as 8 ## published by the Free Software Foundation; version 2 of 9 ## the License. 10 ## 11 ## This program is distributed in the hope that it will be useful, 12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of 13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 ## GNU General Public License for more details. 15 ## 16 ## You should have received a copy of the GNU General Public License 17 ## along with this program; if not, write to the Free Software 18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 19 ## MA 02110-1301 USA 20 ## 21 1 22 driver-y += i82801dx.o 23 driver-y += i82801dx_ac97.o 24 driver-y += i82801dx_ide.o 25 driver-y += i82801dx_lpc.o 26 #driver-y += i82801dx_pci.o 2 27 driver-y += i82801dx_usb.o 3 driver-y += i82801dx_lpc.o4 driver-y += i82801dx_ide.o5 28 driver-y += i82801dx_usb2.o 6 driver-y += i82801dx_ac97.o 7 #driver-y += i82801dx_nic.o 8 #driver-y += i82801dx_pci.o 29 9 30 obj-y += i82801dx_reset.o 31 obj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.o 10 32 11 obj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.o12 33 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smihandler.o -
trunk/src/southbridge/intel/i82801dx/chip.h
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Eric Biederman 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 1 21 #ifndef I82801DX_CHIP_H 2 22 #define I82801DX_CHIP_H 3 23 4 struct southbridge_intel_i82801dx_config 5 { 24 struct southbridge_intel_i82801dx_config { 6 25 int enable_usb; 7 26 int enable_native_ide; … … 25 44 extern struct chip_operations southbridge_intel_i82801dx_ops; 26 45 27 #endif 46 #endif /* I82801DBM_CHIP_H */ -
trunk/src/southbridge/intel/i82801dx/cmos_failover.c
r4381 r5207 1 //kind of cmos_err for ich5 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ron G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 // kind of cmos_err for ICH4 2 22 #define RTC_FAILED (1 <<2) 3 23 #define GEN_PMCON_3 0xa4 4 static void check_cmos_failed(void) 24 static void check_cmos_failed(void) 5 25 { 6 7 uint8_t byte; 8 byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3); 9 if( byte & RTC_FAILED){ 10 //clear bit 1 and bit 2 11 byte = cmos_read(RTC_BOOT_BYTE); 12 byte &= 0x0c; 13 byte |= CONFIG_MAX_REBOOT_CNT << 4; 14 cmos_write(byte, RTC_BOOT_BYTE); 15 } 26 u8 byte; 27 byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); 28 if (byte & RTC_FAILED) { 29 //clear bit 1 and bit 2 30 byte = cmos_read(RTC_BOOT_BYTE); 31 byte &= 0x0c; 32 byte |= CONFIG_MAX_REBOOT_CNT << 4; 33 cmos_write(byte, RTC_BOOT_BYTE); 34 } 16 35 } -
trunk/src/southbridge/intel/i82801dx/i82801dx.c
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ron G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 1 21 #include <console/console.h> 2 22 #include <device/device.h> … … 11 31 uint16_t cur_disable_mask, new_disable_mask; 12 32 13 // 14 unsigned int devfn = PCI_DEVFN(0x1f, 0); 15 device_t lpc_dev = dev_find_slot(0, devfn); 33 // all 82801dbm devices are in bus 0 34 unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc 35 device_t lpc_dev = dev_find_slot(0, devfn); // 0 16 36 if (!lpc_dev) 17 37 return; … … 19 39 // Calculate disable bit position for specified device:function 20 40 // NOTE: For ICH-4, only the following devices can be disabled: 21 // 22 // 41 // D31: F0, F1, F3, F5, F6, 42 // D29: F0, F1, F2, F7 23 43 24 25 44 if (PCI_SLOT(dev->path.pci.devfn) == 31) { 45 index = PCI_FUNC(dev->path.pci.devfn); 26 46 27 47 switch (index) { 28 29 30 31 32 33 34 35 36 37 48 case 0: 49 case 1: 50 case 3: 51 case 5: 52 case 6: 53 bHasDisableBit = 1; 54 break; 55 56 default: 57 break; 38 58 }; 39 59 40 60 if (index == 0) 41 index = 14; 61 index = 14; // D31:F0 bit is an exception 42 62 43 44 63 } else if (PCI_SLOT(dev->path.pci.devfn) == 29) { 64 index = 8 + PCI_FUNC(dev->path.pci.devfn); 45 65 46 if ((PCI_FUNC(dev->path.pci.devfn) < 3) || (PCI_FUNC(dev->path.pci.devfn) == 7)) 66 if ((PCI_FUNC(dev->path.pci.devfn) < 3) 67 || (PCI_FUNC(dev->path.pci.devfn) == 7)) 47 68 bHasDisableBit = 1; 48 69 } 49 70 50 71 if (bHasDisableBit) { 51 72 cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); 52 new_disable_mask = cur_disable_mask & ~(1 <<index);// enable it73 new_disable_mask = cur_disable_mask & ~(1 << index); // enable it 53 74 if (!dev->enabled) { 54 new_disable_mask |= (1 <<index);// disable it75 new_disable_mask |= (1 << index); // disable it 55 76 } 56 77 if (new_disable_mask != cur_disable_mask) { … … 62 83 struct chip_operations southbridge_intel_i82801dx_ops = { 63 84 CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge") 64 .enable_dev = i82801dx_enable,85 .enable_dev = i82801dx_enable, 65 86 }; -
trunk/src/southbridge/intel/i82801dx/i82801dx.h
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ron G. Minnich 5 * Copyright (C) 2004 Eric Biederman 6 * Copyright (C) 2008-2009 coresystems GmbH 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 */ 22 1 23 /* the problem: we have 82801dbm support in fb1, and 82801er in fb2. 2 24 * fb1 code is what we want, fb2 structure is needed however. … … 24 46 25 47 /* 26 000 = Non-combined. P0 is primary master. P1 is secondary master. 27 001 = Non-combined. P0 is secondary master. P1 is primary master. 28 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel 29 disabled. 30 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. 31 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE 32 channel disabled. 33 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. 34 */ 48 * 000 = Non-combined. P0 is primary master. P1 is secondary master. 49 * 001 = Non-combined. P0 is secondary master. P1 is primary master. 50 * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; 51 * Primary IDE channel disabled. 52 * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. 53 * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary 54 * slave; Secondary IDE channel disabled. 55 * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. 56 */ 57 /* PCI Configuration Space (D31:F1) */ 58 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ 59 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ 60 61 /* IDE_TIM bits */ 62 #define IDE_DECODE_ENABLE (1 << 15) 63 64 35 65 36 66 #define PCI_DMA_CFG 0x90 -
trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ronald G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 1 20 2 21 //#define SMBUS_IO_BASE 0x1000 … … 13 32 #define SMBSLVDATA 0xa 14 33 #define SMLINK_PIN_CTL 0xe 15 #define SMBUS_PIN_CTL 0xf 34 #define SMBUS_PIN_CTL 0xf 16 35 17 36 /* Between 1-10 seconds, We should never timeout normally … … 29 48 /* Set smbus enable */ 30 49 pci_write_config8(dev, 0x40, 0x01); 31 /* Set smbus iospace enable */ 50 /* Set smbus iospace enable */ 32 51 pci_write_config16(dev, 0x4, 0x01); 33 /* Disable interrupt generation */ 52 /* Disable interrupt generation */ 34 53 outb(0, SMBUS_IO_BASE + SMBHSTCTL); 35 54 /* clear any lingering errors, so the transaction will run */ 36 55 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 37 56 } 38 39 57 40 58 static inline void smbus_delay(void) … … 54 72 break; 55 73 } 56 } while (--loops);57 return loops ?0:-4;74 } while (--loops); 75 return loops ? 0 : -4; 58 76 } 59 77 … … 69 87 break; 70 88 } 71 if (loops == (SMBUS_TIMEOUT / 2)) {72 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 73 74 } 75 } while (--loops);76 return loops ?0:-2;89 if (loops == (SMBUS_TIMEOUT / 2)) { 90 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 91 SMBUS_IO_BASE + SMBHSTSTAT); 92 } 93 } while (--loops); 94 return loops ? 0 : -2; 77 95 } 78 96 … … 84 102 unsigned char val; 85 103 smbus_delay(); 86 104 87 105 val = inb(SMBUS_IO_BASE + SMBHSTSTAT); 88 if ( 89 break; 90 } 91 if ((val & ~((1 <<6)|(1<<0)) ) != 0) {92 break; 93 } 94 } while (--loops);95 return loops ?0:-3;106 if ((val & 1) == 0) { 107 break; 108 } 109 if ((val & ~((1 << 6) | (1 << 0))) != 0) { 110 break; 111 } 112 } while (--loops); 113 return loops ? 0 : -3; 96 114 } 97 115 … … 102 120 unsigned char byte; 103 121 104 /*print_err("smbus_read_byte\r\n"); */122 /*print_err("smbus_read_byte\r\n"); */ 105 123 if (smbus_wait_until_ready() < 0) { 106 124 print_err_hex8(-2); 107 125 return -2; 108 126 } 109 127 110 128 /* setup transaction */ 111 129 /* disable interrupts */ … … 116 134 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); 117 135 /* set up for a byte data read */ 118 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL); 136 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), 137 SMBUS_IO_BASE + SMBHSTCTL); 119 138 120 139 /* clear any lingering errors, so the transaction will run */ 121 140 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 122 141 123 /* clear the data byte... */142 /* clear the data byte... */ 124 143 outb(0, SMBUS_IO_BASE + SMBHSTDAT0); 125 144 126 145 /* start a byte read, with interrupts disabled */ 127 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); 146 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), 147 SMBUS_IO_BASE + SMBHSTCTL); 128 148 /* poll for it to start */ 129 149 if (smbus_wait_until_active() < 0) { … … 138 158 } 139 159 140 global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 <<6);/* Ignore the In Use Status... */160 global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6); /* Ignore the In Use Status... */ 141 161 142 162 /* read results of transaction */ … … 154 174 return byte; 155 175 } 176 156 177 #if 0 157 static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) 178 static void smbus_write_byte(unsigned device, unsigned address, 179 unsigned char val) 158 180 { 159 181 if (smbus_wait_until_ready() < 0) { … … 162 184 163 185 /* by LYH */ 164 outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT);186 outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT); 165 187 /* set the device I'm talking too */ 166 188 outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR); -
trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ronald G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 1 21 #include <console/console.h> 2 22 #include <device/device.h> … … 6 26 #include "i82801dx.h" 7 27 28 typedef struct southbridge_intel_i82801dx_config config_t; 8 29 9 30 static void ide_init(struct device *dev) 10 31 { 11 #if ICH5_SATA_ADDRESS_MAP<=1 12 /* Enable ide devices so the linux ide driver will work */ 13 uint16_t word; 14 uint8_t byte; 15 int enable_a=1, enable_b=1; 32 /* Get the chip configuration */ 33 config_t *config = dev->chip_info; 16 34 35 /* Enable IDE devices so the Linux IDE driver will work. */ 36 uint16_t ideTimingConfig; 17 37 18 word = pci_read_config16(dev, 0x40); 19 word &= ~((1 << 15)); 20 if (enable_a) { 21 /* Enable first ide interface */ 22 word |= (1<<15); 23 printk_debug("IDE0 "); 38 ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); 39 ideTimingConfig &= ~IDE_DECODE_ENABLE; 40 if (!config || config->ide0_enable) { 41 /* Enable primary IDE interface. */ 42 ideTimingConfig |= IDE_DECODE_ENABLE; 43 printk_debug("IDE0: Primary IDE interface is enabled\n"); 44 } else { 45 printk_info("IDE0: Primary IDE interface is disabled\n"); 24 46 } 25 pci_write_config16(dev, 0x40, word);47 pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); 26 48 27 word = pci_read_config16(dev, 0x42);28 word &= ~((1 << 15));29 if (enable_b) {30 /* Enable secondary ide interface*/31 word |= (1<<15);32 printk_debug("IDE1");33 } 34 pci_write_config16(dev, 0x42, word);35 #endif 36 49 ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); 50 ideTimingConfig &= ~IDE_DECODE_ENABLE; 51 if (!config || config->ide1_enable) { 52 /* Enable secondary IDE interface. */ 53 ideTimingConfig |= IDE_DECODE_ENABLE; 54 printk_debug("IDE1: Secondary IDE interface is enabled\n"); 55 } else { 56 printk_info("IDE1: Secondary IDE interface is disabled\n"); 57 } 58 pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); 37 59 } 38 60 39 static struct device_operations ide_ops 40 .read_resources 41 .set_resources 61 static struct device_operations ide_ops = { 62 .read_resources = pci_dev_read_resources, 63 .set_resources = pci_dev_set_resources, 42 64 .enable_resources = pci_dev_enable_resources, 43 .init 44 .scan_bus 45 .enable 65 .init = ide_init, 66 .scan_bus = 0, 67 .enable = i82801dx_enable, 46 68 }; 47 69 48 static const struct pci_driver ide_driver __pci_driver = { 49 .ops = &ide_ops, 70 /* 82801DB */ 71 static const struct pci_driver i82801db_ide __pci_driver = { 72 .ops = &ide_ops, 50 73 .vendor = PCI_VENDOR_ID_INTEL, 51 .device = PCI_DEVICE_ID_INTEL_82801DBM_IDE,74 .device = 0x24cb, 52 75 }; 53 76 77 /* 82801DBM */ 78 static const struct pci_driver i82801dbm_ide __pci_driver = { 79 .ops = &ide_ops, 80 .vendor = PCI_VENDOR_ID_INTEL, 81 .device = 0x24ca, 82 }; -
trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
r5167 r5207 1 1 /* 2 * (C) 2003 Linux Networx, SuSE Linux AG 3 * (C) 2004 Tyan Computer 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2003 Linux Networx 5 * Copyright (C) 2004 SuSE Linux AG 6 * Copyright (C) 2004 Tyan Computer 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; version 2 of 11 * the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 4 21 */ 22 5 23 #include <console/console.h> 6 24 #include <device/device.h> … … 13 31 #include "i82801dx.h" 14 32 15 16 17 33 #define NMI_OFF 0 18 34 19 void i82801dx_enable_ioapic( struct device *dev) 20 { 21 uint32_t dword; 22 volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000; 23 volatile uint32_t *ioapic_sbd = (volatile uint32_t *)0xfec00010; 24 25 dword = pci_read_config32(dev, GEN_CNTL); 26 dword |= (3 << 7); /* enable ioapic */ 27 dword |= (1 <<13); /* coprocessor error enable */ 28 dword |= (1 << 1); /* delay transaction enable */ 29 dword |= (1 << 2); /* DMA collection buf enable */ 30 pci_write_config32(dev, GEN_CNTL, dword); 31 printk_debug("ioapic southbridge enabled %x\n",dword); 32 *ioapic_sba=0; 33 *ioapic_sbd=(2<<24); 34 //lyh *ioapic_sba=3; 35 //lyh *ioapic_sbd=1; 36 *ioapic_sba=0; 37 dword=*ioapic_sbd; 38 printk_debug("Southbridge apic id = %x\n",dword); 39 if(dword!=(2<<24)) 40 die(""); 41 //lyh *ioapic_sba=3; 42 //lyh dword=*ioapic_sbd; 43 //lyh printk_debug("Southbridge apic DT = %x\n",dword); 44 //lyh if(dword!=1) 45 //lyh die(""); 46 47 48 } 49 void i82801dx_enable_serial_irqs( struct device *dev) 50 { 51 pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); 52 } 53 void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask) 54 { 55 uint16_t word; 56 int i; 57 word = pci_read_config16(dev, PCI_DMA_CFG); 58 word &= ((1 << 10) - (1 << 8)); 59 for(i = 0; i < 8; i++) { 60 if (i == 4) 61 continue; 62 word |= ((mask & (1 << i))? 3:1) << (i*2); 63 } 64 pci_write_config16(dev, PCI_DMA_CFG, word); 65 } 35 void i82801dx_enable_ioapic(struct device *dev) 36 { 37 u32 dword; 38 volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000; 39 volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010; 40 41 dword = pci_read_config32(dev, GEN_CNTL); 42 dword |= (3 << 7); /* enable ioapic */ 43 dword |= (1 << 13); /* coprocessor error enable */ 44 dword |= (1 << 1); /* delay transaction enable */ 45 dword |= (1 << 2); /* DMA collection buf enable */ 46 pci_write_config32(dev, GEN_CNTL, dword); 47 printk_debug("ioapic southbridge enabled %x\n", dword); 48 *ioapic_sba = 0; 49 *ioapic_sbd = (2 << 24); 50 //lyh *ioapic_sba=3; 51 //lyh *ioapic_sbd=1; 52 *ioapic_sba = 0; 53 dword = *ioapic_sbd; 54 printk_debug("Southbridge apic id = %x\n", dword); 55 if (dword != (2 << 24)) 56 die(""); 57 //lyh *ioapic_sba=3; 58 //lyh dword=*ioapic_sbd; 59 //lyh printk_debug("Southbridge apic DT = %x\n",dword); 60 //lyh if(dword!=1) 61 //lyh die(""); 62 63 } 64 65 void i82801dx_enable_serial_irqs(struct device *dev) 66 { 67 pci_write_config8(dev, SERIRQ_CNTL, 68 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); 69 } 70 71 void i82801dx_lpc_route_dma(struct device *dev, u8 mask) 72 { 73 u16 word; 74 int i; 75 word = pci_read_config16(dev, PCI_DMA_CFG); 76 word &= ((1 << 10) - (1 << 8)); 77 for (i = 0; i < 8; i++) { 78 if (i == 4) 79 continue; 80 word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); 81 } 82 pci_write_config16(dev, PCI_DMA_CFG, word); 83 } 84 66 85 void i82801dx_rtc_init(struct device *dev) 67 86 { 68 uint8_t byte; 69 uint32_t dword; 70 int rtc_failed; 71 byte = pci_read_config8(dev, GEN_PMCON_3); 72 rtc_failed = byte & RTC_FAILED; 73 if (rtc_failed) { 74 byte &= ~(1 << 1); /* preserve the power fail state */ 75 pci_write_config8(dev, GEN_PMCON_3, byte); 76 } 77 dword = pci_read_config32(dev, GEN_STS); 78 rtc_failed |= dword & (1 << 2); 79 rtc_init(rtc_failed); 80 } 81 87 u8 byte; 88 u32 dword; 89 int rtc_failed; 90 byte = pci_read_config8(dev, GEN_PMCON_3); 91 rtc_failed = byte & RTC_FAILED; 92 if (rtc_failed) { 93 byte &= ~(1 << 1); /* preserve the power fail state */ 94 pci_write_config8(dev, GEN_PMCON_3, byte); 95 } 96 dword = pci_read_config32(dev, GEN_STS); 97 rtc_failed |= dword & (1 << 2); 98 rtc_init(rtc_failed); 99 } 82 100 83 101 void i82801dx_1f0_misc(struct device *dev) 84 102 { 85 86 87 88 89 90 91 92 93 pci_write_config8(dev, COM_DEC, 0x10);//lyh E0->94 pci_write_config16(dev, LPC_EN, 0x000F);//LYH 000D->103 pci_write_config16(dev, PCICMD, 0x014f); 104 pci_write_config32(dev, PMBASE, 0x00001001); 105 pci_write_config8(dev, ACPI_CNTL, 0x10); 106 pci_write_config32(dev, GPIO_BASE, 0x00001181); 107 pci_write_config8(dev, GPIO_CNTL, 0x10); 108 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); 109 pci_write_config8(dev, PIRQE_ROUT, 0x07); 110 pci_write_config8(dev, RTC_CONF, 0x04); 111 pci_write_config8(dev, COM_DEC, 0x10); //lyh E0-> 112 pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D-> 95 113 } 96 114 … … 99 117 const unsigned long hpet_address = 0xfed0000; 100 118 101 uint32_tdword;102 u int32_tcode = (0 & 0x3);103 104 105 dword |= (1 << 17);/* enable hpet */119 u32 dword; 120 u32 code = (0 & 0x3); 121 122 dword = pci_read_config32(dev, GEN_CNTL); 123 dword |= (1 << 17); /* enable hpet */ 106 124 /*Bits [16:15]Memory Address Range 107 00 FED0_0000h - FED0_03FFh108 01 FED0_1000h - FED0_13FFh109 10 FED0_2000h - FED0_23FFh110 11 FED0_3000h - FED0_33FFh*/111 112 dword &= ~(3 << 15);/* clear it */113 dword |= (code <<15);114 115 printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12));125 00 FED0_0000h - FED0_03FFh 126 01 FED0_1000h - FED0_13FFh 127 10 FED0_2000h - FED0_23FFh 128 11 FED0_3000h - FED0_33FFh */ 129 130 dword &= ~(3 << 15); /* clear it */ 131 dword |= (code << 15); 132 133 printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12)); 116 134 } 117 135 118 136 static void lpc_init(struct device *dev) 119 137 { 120 u int8_tbyte;121 int pwr_on =-1;138 u8 byte; 139 int pwr_on = -1; 122 140 int nmi_option; 123 141 … … 127 145 i82801dx_enable_serial_irqs(dev); 128 146 129 #ifdef SUSPICIOUS_LOOKING_CODE 147 #ifdef SUSPICIOUS_LOOKING_CODE 130 148 // The ICH-4 datasheet does not mention this configuration register. 131 149 // This code may have been inherited (incorrectly) from code for the AMD 766 southbridge, … … 134 152 /* posted memory write enable */ 135 153 byte = pci_read_config8(dev, 0x46); 136 pci_write_config8(dev, 0x46, byte | (1 <<0));154 pci_write_config8(dev, 0x46, byte | (1 << 0)); 137 155 #endif 138 156 139 157 /* power after power fail */ 140 141 142 143 144 145 pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);146 printk_info("set power %s after power fail\n", pwr_on?"on":"off");158 /* FIXME this doesn't work! */ 159 /* Which state do we want to goto after g3 (power restored)? 160 * 0 == S0 Full On 161 * 1 == S5 Soft Off 162 */ 163 pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); 164 printk_info("set power %s after power fail\n", pwr_on ? "on" : "off"); 147 165 #if 0 148 166 /* Enable Error reporting */ … … 154 172 155 173 /* Set up NMI on errors */ 156 157 byte &= ~(1 << 3);/* IOCHK# NMI Enable */158 byte &= ~(1 << 2);/* PCI SERR# Enable */159 160 174 byte = inb(0x61); 175 byte &= ~(1 << 3); /* IOCHK# NMI Enable */ 176 byte &= ~(1 << 2); /* PCI SERR# Enable */ 177 outb(byte, 0x61); 178 byte = inb(0x70); 161 179 nmi_option = NMI_OFF; 162 180 get_option(&nmi_option, "nmi"); 163 if (nmi_option) { 164 byte &= ~(1 << 7);/* set NMI */165 181 if (nmi_option) { 182 byte &= ~(1 << 7); /* set NMI */ 183 outb(byte, 0x70); 166 184 } 167 185 168 186 /* Initialize the real time clock */ 169 187 i82801dx_rtc_init(dev); … … 191 209 res->size = 0x1000; 192 210 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | 193 211 IORESOURCE_ASSIGNED | IORESOURCE_FIXED; 194 212 195 213 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); 196 214 res->base = 0xff800000; 197 res->size = 0x00800000; 215 res->size = 0x00800000; /* 8 MB for flash */ 198 216 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | 199 200 201 res = new_resource(dev, 3); 217 IORESOURCE_ASSIGNED | IORESOURCE_FIXED; 218 219 res = new_resource(dev, 3); /* IOAPIC */ 202 220 res->base = 0xfec00000; 203 221 res->size = 0x00001000; … … 211 229 } 212 230 213 static struct device_operations lpc_ops 214 .read_resources 215 .set_resources 231 static struct device_operations lpc_ops = { 232 .read_resources = i82801dx_lpc_read_resources, 233 .set_resources = pci_dev_set_resources, 216 234 .enable_resources = i82801dx_lpc_enable_resources, 217 .init 218 .scan_bus 219 .enable 235 .init = lpc_init, 236 .scan_bus = scan_static_bus, 237 .enable = i82801dx_enable, 220 238 }; 221 239 222 static const struct pci_driver lpc_driver __pci_driver = { 223 .ops = &lpc_ops, 240 /* 82801DB/DBL */ 241 static const struct pci_driver lpc_driver_db __pci_driver = { 242 .ops = &lpc_ops, 243 .vendor = PCI_VENDOR_ID_INTEL, 244 .device = PCI_DEVICE_ID_INTEL_82801DB_LPC, 245 }; 246 247 /* 82801DBM */ 248 static const struct pci_driver lpc_driver_dbm __pci_driver = { 249 .ops = &lpc_ops, 224 250 .vendor = PCI_VENDOR_ID_INTEL, 225 251 .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC, -
trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ronald G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19 1 20 #include <console/console.h> 2 21 #include <device/device.h> … … 12 31 /* System error enable */ 13 32 dword = pci_read_config32(dev, 0x04); 14 dword |= (1 <<8);/* SERR# Enable */15 dword |= (1 <<6);/* Parity Error Response */33 dword |= (1 << 8); /* SERR# Enable */ 34 dword |= (1 << 6); /* Parity Error Response */ 16 35 pci_write_config32(dev, 0x04, dword); 17 18 36 } 19 37 20 static struct device_operations pci_ops 21 .read_resources 22 .set_resources 38 static struct device_operations pci_ops = { 39 .read_resources = pci_bus_read_resources, 40 .set_resources = pci_dev_set_resources, 23 41 .enable_resources = pci_bus_enable_resources, 24 .init 25 .scan_bus 42 .init = pci_init, 43 .scan_bus = pci_scan_bridge, 26 44 }; 27 45 28 static const struct pci_driver pci_driver __pci_driver = { 29 .ops = &pci_ops, 46 /* 82801DB */ 47 static const struct pci_driver pci_driver_db __pci_driver = { 48 .ops = &pci_ops, 49 .vendor = PCI_VENDOR_ID_INTEL, 50 .device = PCI_DEVICE_ID_INTEL_82801DB_PCI, 51 }; 52 53 /* 82801DBM/DBL */ 54 static const struct pci_driver pci_driver_dbm __pci_driver = { 55 .ops = &pci_ops, 30 56 .vendor = PCI_VENDOR_ID_INTEL, 31 57 .device = PCI_DEVICE_ID_INTEL_82801DBM_PCI, 32 58 }; 33 -
trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ronald G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19 1 20 #include <arch/io.h> 2 21 3 22 void hard_reset(void) 4 23 { 5 6 outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);24 /* Try rebooting through port 0xcf9 */ 25 outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); 7 26 } -
trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ronald G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19 1 20 #include "i82801dx.h" 2 21 #include <smbus.h> … … 7 26 #define PM_DEVFN PCI_DEVFN(0x1f,3) 8 27 9 #if 010 #define SMBUS_IO_BASE 0x100011 #define SMBHSTSTAT 012 #define SMBHSTCTL 213 #define SMBHSTCMD 314 #define SMBHSTADD 415 #define SMBHSTDAT0 516 #define SMBHSTDAT1 617 #define SMBBLKDAT 718 #endif19 20 28 void smbus_enable(void) 21 29 { … … 24 32 pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1); 25 33 /* smbus enable */ 26 pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 34 pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1); 27 35 /* iospace enable */ 28 36 pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1); 29 37 30 31 38 /* Disable interrupt generation */ 39 outb(0, SMBUS_IO_BASE + SMBHSTCTL); 32 40 33 41 } … … 40 48 static void smbus_wait_until_ready(void) 41 49 { 42 while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {50 while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) { 43 51 /* nop */ 44 52 } … … 51 59 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); 52 60 } 53 while ((byte &1) == 1);54 while ((byte & ~1) == 0) {61 while ((byte & 1) == 1); 62 while ((byte & ~1) == 0) { 55 63 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); 56 64 } … … 72 80 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); 73 81 /* set up for a byte data read */ 74 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); 82 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), 83 SMBUS_IO_BASE + SMBHSTCTL); 75 84 76 85 /* clear any lingering errors, so the transaction will run */ 77 86 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 78 87 79 /* clear the data byte... */88 /* clear the data byte... */ 80 89 outb(0, SMBUS_IO_BASE + SMBHSTDAT0); 81 90 82 91 /* start the command */ 83 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); 92 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), 93 SMBUS_IO_BASE + SMBHSTCTL); 84 94 85 95 /* poll for transaction completion */ -
trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
r5177 r5207 4 4 * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org> 5 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 9 10 * 10 11 * This program is distributed in the hope that it will be useful, … … 15 16 * You should have received a copy of the GNU General Public License 16 17 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA18 * 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 19 * MA 02110-1301 USA 19 20 */ 20 21 … … 34 35 35 36 /* Halt the TCO timer, preventing SMI and automatic reboot */ 36 outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT); 37 outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), 38 PMBASE_ADDR + TCOBASE + TCO1_CNT); 37 39 } -
trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c
r5167 r5207 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2004 Ronald G. Minnich 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 19 * MA 02110-1301 USA 20 */ 21 1 22 #include <console/console.h> 2 23 #include <device/device.h> … … 8 29 static void usb_init(struct device *dev) 9 30 { 10 11 12 #if 0 13 uint32_t cmd; 31 u32 cmd; 14 32 printk_debug("USB: Setting up controller.. "); 15 33 cmd = pci_read_config32(dev, PCI_COMMAND); 16 pci_write_config32(dev, PCI_COMMAND, 17 cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 18 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); 19 20 34 pci_write_config32(dev, PCI_COMMAND, 35 cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 36 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); 21 37 printk_debug("done.\n"); 22 #endif23 24 38 } 25 39 26 static struct device_operations usb_ops 27 .read_resources 28 .set_resources 40 static struct device_operations usb_ops = { 41 .read_resources = pci_dev_read_resources, 42 .set_resources = pci_dev_set_resources, 29 43 .enable_resources = pci_dev_enable_resources, 30 .init 31 .scan_bus 32 .enable 44 .init = usb_init, 45 .scan_bus = 0, 46 .enable = i82801dx_enable, 33 47 }; 34 48 49 /* 82801DB/DBL/DBM USB1 */ 35 50 static const struct pci_driver usb_driver_1 __pci_driver = { 36 .ops 51 .ops = &usb_ops, 37 52 .vendor = PCI_VENDOR_ID_INTEL, 38 .device = PCI_DEVICE_ID_INTEL_82801DB M_USB1,53 .device = PCI_DEVICE_ID_INTEL_82801DB_USB1, 39 54 }; 55 56 /* 82801DB/DBL/DBM USB2 */ 40 57 static const struct pci_driver usb_driver_2 __pci_driver = { 41 .ops= &usb_ops,42 43 .device = PCI_DEVICE_ID_INTEL_82801DB M_USB2,58 .ops = &usb_ops, 59 .vendor = PCI_VENDOR_ID_INTEL, 60 .device = PCI_DEVICE_ID_INTEL_82801DB_USB2, 44 61 }; 62 63 /* 82801DB/DBL/DBM USB3 */ 45 64 static const struct pci_driver usb_driver_3 __pci_driver = { 46 .ops= &usb_ops,47 48 .device = PCI_DEVICE_ID_INTEL_82801DB M_USB3,65 .ops = &usb_ops, 66 .vendor = PCI_VENDOR_ID_INTEL, 67 .device = PCI_DEVICE_ID_INTEL_82801DB_USB3, 49 68 }; -
trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c
r5167 r5207 1 //2003 Copywright Tyan 1 /* 2 * This file is part of the coreboot project. 3 * 4 * Copyright (C) 2003 Tyan 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; version 2 of 9 * the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 19 * MA 02110-1301 USA 20 */ 2 21 3 22 #include <console/console.h> … … 10 29 static void usb2_init(struct device *dev) 11 30 { 12 13 14 #if 0 15 uint32_t cmd; 31 u32 cmd; 16 32 printk_debug("USB: Setting up controller.. "); 17 33 cmd = pci_read_config32(dev, PCI_COMMAND); 18 pci_write_config32(dev, PCI_COMMAND, 19 cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 20 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); 21 22 34 pci_write_config32(dev, PCI_COMMAND, 35 cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 36 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); 23 37 printk_debug("done.\n"); 24 #endif25 38 } 26 39 27 static struct device_operations usb2_ops 28 .read_resources 29 .set_resources 40 static struct device_operations usb2_ops = { 41 .read_resources = pci_dev_read_resources, 42 .set_resources = pci_dev_set_resources, 30 43 .enable_resources = pci_dev_enable_resources, 31 .init 32 .scan_bus 33 .enable 44 .init = usb2_init, 45 .scan_bus = 0, 46 .enable = i82801dx_enable, 34 47 }; 35 48 49 /* 82801DB/DBM USB 2.0 */ 36 50 static const struct pci_driver usb2_driver __pci_driver = { 37 .ops 51 .ops = &usb2_ops, 38 52 .vendor = PCI_VENDOR_ID_INTEL, 39 .device = PCI_DEVICE_ID_INTEL_82801DB M_EHCI,53 .device = PCI_DEVICE_ID_INTEL_82801DB_EHCI, 40 54 };
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