Changeset 5207


Ignore:
Timestamp:
Mar 14, 2010, 6:01:08 PM (5 years ago)
Author:
stepan
Message:

ICH4 update, fix ATA init, drop SATA (chipset doesn't have SATA)
fix some PCI IDs, enable USB bus mastering, add some license headers, ...

LPC code needs another look, but I think we're getting there.

Signed-off-by: Stefan Reinauer <stepan@…>
Acked-by: Joseph Smith <joe@…>

Location:
trunk/src/southbridge/intel/i82801dx
Files:
2 deleted
15 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/southbridge/intel/i82801dx/Kconfig

    r5177 r5207  
     1##
     2## This file is part of the coreboot project.
     3##
     4## Copyright (C) 2008-2009 coresystems GmbH
     5##
     6## This program is free software; you can redistribute it and/or
     7## modify it under the terms of the GNU General Public License as
     8## published by the Free Software Foundation; version 2 of
     9## the License.
     10##
     11## This program is distributed in the hope that it will be useful,
     12## but WITHOUT ANY WARRANTY; without even the implied warranty of
     13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14## GNU General Public License for more details.
     15##
     16## You should have received a copy of the GNU General Public License
     17## along with this program; if not, write to the Free Software
     18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
     19## MA 02110-1301 USA
     20##
     21
    122config SOUTHBRIDGE_INTEL_I82801DX
    223        bool
  • trunk/src/southbridge/intel/i82801dx/Makefile.inc

    r5177 r5207  
     1##
     2## This file is part of the coreboot project.
     3##
     4## Copyright (C) 2008-2009 coresystems GmbH
     5##
     6## This program is free software; you can redistribute it and/or
     7## modify it under the terms of the GNU General Public License as
     8## published by the Free Software Foundation; version 2 of
     9## the License.
     10##
     11## This program is distributed in the hope that it will be useful,
     12## but WITHOUT ANY WARRANTY; without even the implied warranty of
     13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14## GNU General Public License for more details.
     15##
     16## You should have received a copy of the GNU General Public License
     17## along with this program; if not, write to the Free Software
     18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
     19## MA 02110-1301 USA
     20##
     21
    122driver-y += i82801dx.o
     23driver-y += i82801dx_ac97.o
     24driver-y += i82801dx_ide.o
     25driver-y += i82801dx_lpc.o
     26#driver-y += i82801dx_pci.o
    227driver-y += i82801dx_usb.o
    3 driver-y += i82801dx_lpc.o
    4 driver-y += i82801dx_ide.o
    528driver-y += i82801dx_usb2.o
    6 driver-y += i82801dx_ac97.o
    7 #driver-y += i82801dx_nic.o
    8 #driver-y += i82801dx_pci.o
     29
    930obj-y += i82801dx_reset.o
     31obj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.o
    1032
    11 obj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.o
    1233smmobj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smihandler.o
  • trunk/src/southbridge/intel/i82801dx/chip.h

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Eric Biederman
     5 *
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, write to the Free Software
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
     19 */
     20
    121#ifndef I82801DX_CHIP_H
    222#define I82801DX_CHIP_H
    323
    4 struct southbridge_intel_i82801dx_config
    5 {
     24struct southbridge_intel_i82801dx_config {
    625        int enable_usb;
    726        int enable_native_ide;
     
    2544extern struct chip_operations southbridge_intel_i82801dx_ops;
    2645
    27 #endif /* I82801DBM_CHIP_H */
     46#endif                          /* I82801DBM_CHIP_H */
  • trunk/src/southbridge/intel/i82801dx/cmos_failover.c

    r4381 r5207  
    1 //kind of cmos_err for ich5
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ron G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, write to the Free Software
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
     19 */
     20
     21// kind of cmos_err for ICH4
    222#define RTC_FAILED    (1 <<2)
    323#define GEN_PMCON_3     0xa4
    4 static void check_cmos_failed(void) 
     24static void check_cmos_failed(void)
    525{
    6 
    7                 uint8_t byte;
    8                 byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
    9                 if( byte & RTC_FAILED){
    10 //clear bit 1 and bit 2
    11                         byte = cmos_read(RTC_BOOT_BYTE);
    12                         byte &= 0x0c;
    13                         byte |= CONFIG_MAX_REBOOT_CNT << 4;
    14                         cmos_write(byte, RTC_BOOT_BYTE);
    15                 }
     26        u8 byte;
     27        byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
     28        if (byte & RTC_FAILED) {
     29                //clear bit 1 and bit 2
     30                byte = cmos_read(RTC_BOOT_BYTE);
     31                byte &= 0x0c;
     32                byte |= CONFIG_MAX_REBOOT_CNT << 4;
     33                cmos_write(byte, RTC_BOOT_BYTE);
     34        }
    1635}
  • trunk/src/southbridge/intel/i82801dx/i82801dx.c

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ron G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, write to the Free Software
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
     19 */
     20
    121#include <console/console.h>
    222#include <device/device.h>
     
    1131        uint16_t cur_disable_mask, new_disable_mask;
    1232
    13 //      all 82801dbm devices are in bus 0
    14         unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
    15         device_t lpc_dev = dev_find_slot(0, devfn); // 0
     33//      all 82801dbm devices are in bus 0
     34        unsigned int devfn = PCI_DEVFN(0x1f, 0);        // lpc
     35        device_t lpc_dev = dev_find_slot(0, devfn);     // 0
    1636        if (!lpc_dev)
    1737                return;
     
    1939        // Calculate disable bit position for specified device:function
    2040        // NOTE: For ICH-4, only the following devices can be disabled:
    21         //              D31: F0, F1, F3, F5, F6,
    22         //              D29: F0, F1, F2, F7
     41        //              D31: F0, F1, F3, F5, F6,
     42        //              D29: F0, F1, F2, F7
    2343
    24     if (PCI_SLOT(dev->path.pci.devfn) == 31) {
    25         index = PCI_FUNC(dev->path.pci.devfn);
     44        if (PCI_SLOT(dev->path.pci.devfn) == 31) {
     45                index = PCI_FUNC(dev->path.pci.devfn);
    2646
    2747                switch (index) {
    28                         case 0:
    29                         case 1:
    30                         case 3:
    31                         case 5:
    32                         case 6:
    33                                 bHasDisableBit = 1;
    34                                 break;
    35                        
    36                         default:
    37                                 break;
     48                case 0:
     49                case 1:
     50                case 3:
     51                case 5:
     52                case 6:
     53                        bHasDisableBit = 1;
     54                        break;
     55
     56                default:
     57                        break;
    3858                };
    39                
     59
    4060                if (index == 0)
    41                         index = 14;             // D31:F0 bit is an exception
     61                        index = 14;     // D31:F0 bit is an exception
    4262
    43     } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
    44         index = 8 + PCI_FUNC(dev->path.pci.devfn);
     63        } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
     64                index = 8 + PCI_FUNC(dev->path.pci.devfn);
    4565
    46                 if ((PCI_FUNC(dev->path.pci.devfn) < 3) || (PCI_FUNC(dev->path.pci.devfn) == 7))
     66                if ((PCI_FUNC(dev->path.pci.devfn) < 3)
     67                    || (PCI_FUNC(dev->path.pci.devfn) == 7))
    4768                        bHasDisableBit = 1;
    48     }
     69        }
    4970
    5071        if (bHasDisableBit) {
    5172                cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
    52                 new_disable_mask = cur_disable_mask & ~(1<<index);              // enable it
     73                new_disable_mask = cur_disable_mask & ~(1 << index);    // enable it
    5374                if (!dev->enabled) {
    54                         new_disable_mask |= (1<<index);  // disable it
     75                        new_disable_mask |= (1 << index);       // disable it
    5576                }
    5677                if (new_disable_mask != cur_disable_mask) {
     
    6283struct chip_operations southbridge_intel_i82801dx_ops = {
    6384        CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge")
    64         .enable_dev = i82801dx_enable,
     85            .enable_dev = i82801dx_enable,
    6586};
  • trunk/src/southbridge/intel/i82801dx/i82801dx.h

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ron G. Minnich
     5 * Copyright (C) 2004 Eric Biederman
     6 * Copyright (C) 2008-2009 coresystems GmbH
     7 *
     8 * This program is free software; you can redistribute it and/or
     9 * modify it under the terms of the GNU General Public License as
     10 * published by the Free Software Foundation; version 2 of
     11 * the License.
     12 *
     13 * This program is distributed in the hope that it will be useful,
     14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16 * GNU General Public License for more details.
     17 *
     18 * You should have received a copy of the GNU General Public License
     19 * along with this program; if not, write to the Free Software
     20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
     21 */
     22
    123/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
    224 * fb1 code is what we want, fb2 structure is needed however.
     
    2446
    2547/*
    26 000 = Non-combined. P0 is primary master. P1 is secondary master.
    27 001 = Non-combined. P0 is secondary master. P1 is primary master.
    28 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
    29 disabled.
    30 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
    31 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
    32 channel disabled.
    33 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
    34 */
     48 * 000 = Non-combined. P0 is primary master. P1 is secondary master.
     49 * 001 = Non-combined. P0 is secondary master. P1 is primary master.
     50 * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;
     51 *       Primary IDE channel disabled.
     52 * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
     53 * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary
     54 *       slave; Secondary IDE channel disabled.
     55 * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
     56 */
     57/* PCI Configuration Space (D31:F1) */
     58#define IDE_TIM_PRI             0x40    /* IDE timings, primary */
     59#define IDE_TIM_SEC             0x42    /* IDE timings, secondary */
     60
     61/* IDE_TIM bits */
     62#define IDE_DECODE_ENABLE       (1 << 15)
     63
     64
    3565
    3666#define PCI_DMA_CFG     0x90
  • trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ronald G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, write to the Free Software
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
     19 */
    120
    221//#define SMBUS_IO_BASE 0x1000
     
    1332#define SMBSLVDATA 0xa
    1433#define SMLINK_PIN_CTL 0xe
    15 #define SMBUS_PIN_CTL  0xf 
     34#define SMBUS_PIN_CTL  0xf
    1635
    1736/* Between 1-10 seconds, We should never timeout normally
     
    2948        /* Set smbus enable */
    3049        pci_write_config8(dev, 0x40, 0x01);
    31         /* Set smbus iospace enable */ 
     50        /* Set smbus iospace enable */
    3251        pci_write_config16(dev, 0x4, 0x01);
    33         /* Disable interrupt generation */ 
     52        /* Disable interrupt generation */
    3453        outb(0, SMBUS_IO_BASE + SMBHSTCTL);
    3554        /* clear any lingering errors, so the transaction will run */
    3655        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
    3756}
    38 
    3957
    4058static inline void smbus_delay(void)
     
    5472                        break;
    5573                }
    56         } while(--loops);
    57         return loops?0:-4;
     74        } while (--loops);
     75        return loops ? 0 : -4;
    5876}
    5977
     
    6987                        break;
    7088                }
    71                 if(loops == (SMBUS_TIMEOUT / 2)) {
    72                         outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 
    73                                 SMBUS_IO_BASE + SMBHSTSTAT);
    74                 }
    75         } while(--loops);
    76         return loops?0:-2;
     89                if (loops == (SMBUS_TIMEOUT / 2)) {
     90                        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
     91                             SMBUS_IO_BASE + SMBHSTSTAT);
     92                }
     93        } while (--loops);
     94        return loops ? 0 : -2;
    7795}
    7896
     
    84102                unsigned char val;
    85103                smbus_delay();
    86                
     104
    87105                val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
    88                 if ( (val & 1) == 0) {
    89                         break;
    90                 }
    91                 if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
    92                         break;
    93                 }
    94         } while(--loops);
    95         return loops?0:-3;
     106                if ((val & 1) == 0) {
     107                        break;
     108                }
     109                if ((val & ~((1 << 6) | (1 << 0))) != 0) {
     110                        break;
     111                }
     112        } while (--loops);
     113        return loops ? 0 : -3;
    96114}
    97115
     
    102120        unsigned char byte;
    103121
    104         /*print_err("smbus_read_byte\r\n");*/
     122        /*print_err("smbus_read_byte\r\n"); */
    105123        if (smbus_wait_until_ready() < 0) {
    106124                print_err_hex8(-2);
    107125                return -2;
    108126        }
    109        
     127
    110128        /* setup transaction */
    111129        /* disable interrupts */
     
    116134        outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
    117135        /* set up for a byte data read */
    118         outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
     136        outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
     137             SMBUS_IO_BASE + SMBHSTCTL);
    119138
    120139        /* clear any lingering errors, so the transaction will run */
    121140        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
    122141
    123         /* clear the data byte...*/
     142        /* clear the data byte... */
    124143        outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
    125144
    126145        /* start a byte read, with interrupts disabled */
    127         outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
     146        outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
     147             SMBUS_IO_BASE + SMBHSTCTL);
    128148        /* poll for it to start */
    129149        if (smbus_wait_until_active() < 0) {
     
    138158        }
    139159
    140         global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
     160        global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6);   /* Ignore the In Use Status... */
    141161
    142162        /* read results of transaction */
     
    154174        return byte;
    155175}
     176
    156177#if 0
    157 static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
     178static void smbus_write_byte(unsigned device, unsigned address,
     179                             unsigned char val)
    158180{
    159181        if (smbus_wait_until_ready() < 0) {
     
    162184
    163185        /* by LYH */
    164         outb(0x37,SMBUS_IO_BASE + SMBHSTSTAT);
     186        outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT);
    165187        /* set the device I'm talking too */
    166188        outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
  • trunk/src/southbridge/intel/i82801dx/i82801dx_ide.c

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ronald G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, write to the Free Software
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
     19 */
     20
    121#include <console/console.h>
    222#include <device/device.h>
     
    626#include "i82801dx.h"
    727
     28typedef struct southbridge_intel_i82801dx_config config_t;
    829
    930static void ide_init(struct device *dev)
    1031{
    11 #if ICH5_SATA_ADDRESS_MAP<=1
    12         /* Enable ide devices so the linux ide driver will work */
    13         uint16_t word;
    14         uint8_t byte;
    15         int enable_a=1, enable_b=1;
     32        /* Get the chip configuration */
     33        config_t *config = dev->chip_info;
    1634
     35        /* Enable IDE devices so the Linux IDE driver will work. */
     36        uint16_t ideTimingConfig;
    1737
    18         word = pci_read_config16(dev, 0x40);
    19         word &= ~((1 << 15));
    20         if (enable_a) {
    21                 /* Enable first ide interface */
    22                 word |= (1<<15);
    23                 printk_debug("IDE0 ");
     38        ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
     39        ideTimingConfig &= ~IDE_DECODE_ENABLE;
     40        if (!config || config->ide0_enable) {
     41                /* Enable primary IDE interface. */
     42                ideTimingConfig |= IDE_DECODE_ENABLE;
     43                printk_debug("IDE0: Primary IDE interface is enabled\n");
     44        } else {
     45                printk_info("IDE0: Primary IDE interface is disabled\n");
    2446        }
    25         pci_write_config16(dev, 0x40, word);
     47        pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
    2648
    27         word = pci_read_config16(dev, 0x42);
    28         word &= ~((1 << 15));
    29         if (enable_b) {
    30                 /* Enable secondary ide interface */
    31                 word |= (1<<15);
    32                 printk_debug("IDE1 ");
    33         }
    34         pci_write_config16(dev, 0x42, word);
    35 #endif
    36 
     49        ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
     50        ideTimingConfig &= ~IDE_DECODE_ENABLE;
     51        if (!config || config->ide1_enable) {
     52                /* Enable secondary IDE interface. */
     53                ideTimingConfig |= IDE_DECODE_ENABLE;
     54                printk_debug("IDE1: Secondary IDE interface is enabled\n");
     55        } else {
     56                printk_info("IDE1: Secondary IDE interface is disabled\n");
     57        }
     58        pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
    3759}
    3860
    39 static struct device_operations ide_ops  = {
    40         .read_resources   = pci_dev_read_resources,
    41         .set_resources    = pci_dev_set_resources,
     61static struct device_operations ide_ops = {
     62        .read_resources = pci_dev_read_resources,
     63        .set_resources = pci_dev_set_resources,
    4264        .enable_resources = pci_dev_enable_resources,
    43         .init             = ide_init,
    44         .scan_bus         = 0,
    45         .enable           = i82801dx_enable,
     65        .init = ide_init,
     66        .scan_bus = 0,
     67        .enable = i82801dx_enable,
    4668};
    4769
    48 static const struct pci_driver ide_driver __pci_driver = {
    49         .ops    = &ide_ops,
     70/* 82801DB */
     71static const struct pci_driver i82801db_ide __pci_driver = {
     72        .ops = &ide_ops,
    5073        .vendor = PCI_VENDOR_ID_INTEL,
    51         .device = PCI_DEVICE_ID_INTEL_82801DBM_IDE,
     74        .device = 0x24cb,
    5275};
    5376
     77/* 82801DBM */
     78static const struct pci_driver i82801dbm_ide __pci_driver = {
     79        .ops = &ide_ops,
     80        .vendor = PCI_VENDOR_ID_INTEL,
     81        .device = 0x24ca,
     82};
  • trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c

    r5167 r5207  
    11/*
    2  * (C) 2003 Linux Networx, SuSE Linux AG
    3  * (C) 2004 Tyan Computer
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2003 Linux Networx
     5 * Copyright (C) 2004 SuSE Linux AG
     6 * Copyright (C) 2004 Tyan Computer
     7 *
     8 * This program is free software; you can redistribute it and/or
     9 * modify it under the terms of the GNU General Public License as
     10 * published by the Free Software Foundation; version 2 of
     11 * the License.
     12 *
     13 * This program is distributed in the hope that it will be useful,
     14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16 * GNU General Public License for more details.
     17 *
     18 * You should have received a copy of the GNU General Public License
     19 * along with this program; if not, write to the Free Software
     20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
    421 */
     22
    523#include <console/console.h>
    624#include <device/device.h>
     
    1331#include "i82801dx.h"
    1432
    15 
    16 
    1733#define NMI_OFF 0
    1834
    19 void i82801dx_enable_ioapic( struct device *dev)
    20 {
    21         uint32_t dword;
    22         volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000;
    23         volatile uint32_t *ioapic_sbd = (volatile uint32_t *)0xfec00010;
    24 
    25         dword = pci_read_config32(dev, GEN_CNTL);
    26         dword |= (3 << 7); /* enable ioapic */
    27         dword |= (1 <<13); /* coprocessor error enable */
    28         dword |= (1 << 1); /* delay transaction enable */
    29         dword |= (1 << 2); /* DMA collection buf enable */
    30         pci_write_config32(dev, GEN_CNTL, dword);
    31         printk_debug("ioapic southbridge enabled %x\n",dword);
    32         *ioapic_sba=0;
    33         *ioapic_sbd=(2<<24);
    34         //lyh *ioapic_sba=3;
    35         //lyh *ioapic_sbd=1;   
    36         *ioapic_sba=0;
    37         dword=*ioapic_sbd;
    38         printk_debug("Southbridge apic id = %x\n",dword);
    39         if(dword!=(2<<24))
    40                 die("");
    41         //lyh *ioapic_sba=3;
    42         //lyh dword=*ioapic_sbd;
    43         //lyh printk_debug("Southbridge apic DT = %x\n",dword);
    44         //lyh if(dword!=1)
    45         //lyh   die("");
    46 
    47 
    48 }
    49 void i82801dx_enable_serial_irqs( struct device *dev)
    50 {
    51         pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
    52 }
    53 void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask)
    54 {
    55         uint16_t word;
    56         int i;
    57         word = pci_read_config16(dev, PCI_DMA_CFG);
    58         word &= ((1 << 10) - (1 << 8));
    59         for(i = 0; i < 8; i++) {
    60                 if (i == 4)
    61                         continue;
    62                 word |= ((mask & (1 << i))? 3:1) << (i*2);
    63         }
    64         pci_write_config16(dev, PCI_DMA_CFG, word);
    65 }
     35void i82801dx_enable_ioapic(struct device *dev)
     36{
     37        u32 dword;
     38        volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000;
     39        volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010;
     40
     41        dword = pci_read_config32(dev, GEN_CNTL);
     42        dword |= (3 << 7);      /* enable ioapic */
     43        dword |= (1 << 13);     /* coprocessor error enable */
     44        dword |= (1 << 1);      /* delay transaction enable */
     45        dword |= (1 << 2);      /* DMA collection buf enable */
     46        pci_write_config32(dev, GEN_CNTL, dword);
     47        printk_debug("ioapic southbridge enabled %x\n", dword);
     48        *ioapic_sba = 0;
     49        *ioapic_sbd = (2 << 24);
     50        //lyh *ioapic_sba=3;
     51        //lyh *ioapic_sbd=1;   
     52        *ioapic_sba = 0;
     53        dword = *ioapic_sbd;
     54        printk_debug("Southbridge apic id = %x\n", dword);
     55        if (dword != (2 << 24))
     56                die("");
     57        //lyh *ioapic_sba=3;
     58        //lyh dword=*ioapic_sbd;
     59        //lyh printk_debug("Southbridge apic DT = %x\n",dword);
     60        //lyh if(dword!=1)
     61        //lyh   die("");
     62
     63}
     64
     65void i82801dx_enable_serial_irqs(struct device *dev)
     66{
     67        pci_write_config8(dev, SERIRQ_CNTL,
     68                          (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
     69}
     70
     71void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
     72{
     73        u16 word;
     74        int i;
     75        word = pci_read_config16(dev, PCI_DMA_CFG);
     76        word &= ((1 << 10) - (1 << 8));
     77        for (i = 0; i < 8; i++) {
     78                if (i == 4)
     79                        continue;
     80                word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
     81        }
     82        pci_write_config16(dev, PCI_DMA_CFG, word);
     83}
     84
    6685void i82801dx_rtc_init(struct device *dev)
    6786{
    68         uint8_t byte;
    69         uint32_t dword;
    70         int rtc_failed;
    71         byte = pci_read_config8(dev, GEN_PMCON_3);
    72         rtc_failed = byte & RTC_FAILED;
    73         if (rtc_failed) {
    74                 byte &= ~(1 << 1); /* preserve the power fail state */
    75                 pci_write_config8(dev, GEN_PMCON_3, byte);
    76         }
    77         dword = pci_read_config32(dev, GEN_STS);
    78         rtc_failed |= dword & (1 << 2);
    79         rtc_init(rtc_failed);
    80 }
    81 
     87        u8 byte;
     88        u32 dword;
     89        int rtc_failed;
     90        byte = pci_read_config8(dev, GEN_PMCON_3);
     91        rtc_failed = byte & RTC_FAILED;
     92        if (rtc_failed) {
     93                byte &= ~(1 << 1);      /* preserve the power fail state */
     94                pci_write_config8(dev, GEN_PMCON_3, byte);
     95        }
     96        dword = pci_read_config32(dev, GEN_STS);
     97        rtc_failed |= dword & (1 << 2);
     98        rtc_init(rtc_failed);
     99}
    82100
    83101void i82801dx_1f0_misc(struct device *dev)
    84102{
    85         pci_write_config16(dev, PCICMD, 0x014f);
    86         pci_write_config32(dev, PMBASE, 0x00001001);
    87         pci_write_config8(dev, ACPI_CNTL, 0x10);
    88         pci_write_config32(dev, GPIO_BASE, 0x00001181);
    89         pci_write_config8(dev, GPIO_CNTL, 0x10);
    90         pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
    91         pci_write_config8(dev, PIRQE_ROUT, 0x07);
    92         pci_write_config8(dev, RTC_CONF, 0x04);
    93         pci_write_config8(dev, COM_DEC, 0x10);  //lyh E0->
    94         pci_write_config16(dev, LPC_EN, 0x000F);  //LYH 000D->
     103        pci_write_config16(dev, PCICMD, 0x014f);
     104        pci_write_config32(dev, PMBASE, 0x00001001);
     105        pci_write_config8(dev, ACPI_CNTL, 0x10);
     106        pci_write_config32(dev, GPIO_BASE, 0x00001181);
     107        pci_write_config8(dev, GPIO_CNTL, 0x10);
     108        pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
     109        pci_write_config8(dev, PIRQE_ROUT, 0x07);
     110        pci_write_config8(dev, RTC_CONF, 0x04);
     111        pci_write_config8(dev, COM_DEC, 0x10);  //lyh E0->
     112        pci_write_config16(dev, LPC_EN, 0x000F);        //LYH 000D->
    95113}
    96114
     
    99117        const unsigned long hpet_address = 0xfed0000;
    100118
    101         uint32_t dword;
    102         uint32_t code = (0 & 0x3);
    103        
    104         dword = pci_read_config32(dev, GEN_CNTL);
    105         dword |= (1 << 17); /* enable hpet */
     119        u32 dword;
     120        u32 code = (0 & 0x3);
     121
     122        dword = pci_read_config32(dev, GEN_CNTL);
     123        dword |= (1 << 17);     /* enable hpet */
    106124        /*Bits [16:15]Memory Address Range
    107         00 FED0_0000h - FED0_03FFh
    108         01 FED0_1000h - FED0_13FFh
    109         10 FED0_2000h - FED0_23FFh
    110         11 FED0_3000h - FED0_33FFh*/
    111 
    112         dword &= ~(3 << 15); /* clear it */
    113         dword |= (code<<15);
    114 
    115         printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
     125           00 FED0_0000h - FED0_03FFh
     126           01 FED0_1000h - FED0_13FFh
     127           10 FED0_2000h - FED0_23FFh
     128           11 FED0_3000h - FED0_33FFh */
     129
     130        dword &= ~(3 << 15);    /* clear it */
     131        dword |= (code << 15);
     132
     133        printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12));
    116134}
    117135
    118136static void lpc_init(struct device *dev)
    119137{
    120         uint8_t byte;
    121         int pwr_on=-1;
     138        u8 byte;
     139        int pwr_on = -1;
    122140        int nmi_option;
    123141
     
    127145        i82801dx_enable_serial_irqs(dev);
    128146
    129 #ifdef SUSPICIOUS_LOOKING_CODE 
     147#ifdef SUSPICIOUS_LOOKING_CODE
    130148        // The ICH-4 datasheet does not mention this configuration register.
    131149        // This code may have been inherited (incorrectly) from code for the AMD 766 southbridge,
     
    134152        /* posted memory write enable */
    135153        byte = pci_read_config8(dev, 0x46);
    136         pci_write_config8(dev, 0x46, byte | (1<<0));
     154        pci_write_config8(dev, 0x46, byte | (1 << 0));
    137155#endif
    138156
    139157        /* power after power fail */
    140                 /* FIXME this doesn't work! */
    141         /* Which state do we want to goto after g3 (power restored)?
    142         * 0 == S0 Full On
    143         * 1 == S5 Soft Off
    144         */
    145         pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);
    146         printk_info("set power %s after power fail\n", pwr_on?"on":"off");
     158        /* FIXME this doesn't work! */
     159        /* Which state do we want to goto after g3 (power restored)?
     160        * 0 == S0 Full On
     161        * 1 == S5 Soft Off
     162        */
     163        pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
     164        printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
    147165#if 0
    148166        /* Enable Error reporting */
     
    154172
    155173        /* Set up NMI on errors */
    156     byte = inb(0x61);
    157     byte &= ~(1 << 3); /* IOCHK# NMI Enable */
    158     byte &= ~(1 << 2); /* PCI SERR# Enable */
    159     outb(byte, 0x61);
    160     byte = inb(0x70);
     174        byte = inb(0x61);
     175        byte &= ~(1 << 3);      /* IOCHK# NMI Enable */
     176        byte &= ~(1 << 2);      /* PCI SERR# Enable */
     177        outb(byte, 0x61);
     178        byte = inb(0x70);
    161179        nmi_option = NMI_OFF;
    162180        get_option(&nmi_option, "nmi");
    163         if (nmi_option) {                       
    164         byte &= ~(1 << 7); /* set NMI */
    165         outb(byte, 0x70);
     181        if (nmi_option) {
     182                byte &= ~(1 << 7);      /* set NMI */
     183                outb(byte, 0x70);
    166184        }
    167        
     185
    168186        /* Initialize the real time clock */
    169187        i82801dx_rtc_init(dev);
     
    191209        res->size = 0x1000;
    192210        res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
    193                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
     211            IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
    194212
    195213        res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
    196214        res->base = 0xff800000;
    197         res->size = 0x00800000; /* 8 MB for flash */
     215        res->size = 0x00800000; /* 8 MB for flash */
    198216        res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
    199                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
    200 
    201         res = new_resource(dev, 3); /* IOAPIC */
     217            IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
     218
     219        res = new_resource(dev, 3);     /* IOAPIC */
    202220        res->base = 0xfec00000;
    203221        res->size = 0x00001000;
     
    211229}
    212230
    213 static struct device_operations lpc_ops  = {
    214         .read_resources   = i82801dx_lpc_read_resources,
    215         .set_resources    = pci_dev_set_resources,
     231static struct device_operations lpc_ops = {
     232        .read_resources = i82801dx_lpc_read_resources,
     233        .set_resources = pci_dev_set_resources,
    216234        .enable_resources = i82801dx_lpc_enable_resources,
    217         .init             = lpc_init,
    218         .scan_bus         = scan_static_bus,
    219         .enable           = i82801dx_enable,
     235        .init = lpc_init,
     236        .scan_bus = scan_static_bus,
     237        .enable = i82801dx_enable,
    220238};
    221239
    222 static const struct pci_driver lpc_driver __pci_driver = {
    223         .ops    = &lpc_ops,
     240/* 82801DB/DBL */
     241static const struct pci_driver lpc_driver_db __pci_driver = {
     242        .ops = &lpc_ops,
     243        .vendor = PCI_VENDOR_ID_INTEL,
     244        .device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
     245};
     246
     247/* 82801DBM */
     248static const struct pci_driver lpc_driver_dbm __pci_driver = {
     249        .ops = &lpc_ops,
    224250        .vendor = PCI_VENDOR_ID_INTEL,
    225251        .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,
  • trunk/src/southbridge/intel/i82801dx/i82801dx_pci.c

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ronald G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or modify
     7 * it under the terms of the GNU General Public License as published by
     8 * the Free Software Foundation; version 2 of the License.
     9 *
     10 * This program is distributed in the hope that it will be useful,
     11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     13 * GNU General Public License for more details.
     14 *
     15 * You should have received a copy of the GNU General Public License
     16 * along with this program; if not, write to the Free Software
     17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
     18 */
     19
    120#include <console/console.h>
    221#include <device/device.h>
     
    1231        /* System error enable */
    1332        dword = pci_read_config32(dev, 0x04);
    14         dword |= (1<<8); /* SERR# Enable */
    15         dword |= (1<<6); /* Parity Error Response */
     33        dword |= (1 << 8);      /* SERR# Enable */
     34        dword |= (1 << 6);      /* Parity Error Response */
    1635        pci_write_config32(dev, 0x04, dword);
    17 
    1836}
    1937
    20 static struct device_operations pci_ops  = {
    21         .read_resources   = pci_bus_read_resources,
    22         .set_resources    = pci_dev_set_resources,
     38static struct device_operations pci_ops = {
     39        .read_resources = pci_bus_read_resources,
     40        .set_resources = pci_dev_set_resources,
    2341        .enable_resources = pci_bus_enable_resources,
    24         .init             = pci_init,
    25         .scan_bus         = pci_scan_bridge,
     42        .init = pci_init,
     43        .scan_bus = pci_scan_bridge,
    2644};
    2745
    28 static const struct pci_driver pci_driver __pci_driver = {
    29         .ops    = &pci_ops,
     46/* 82801DB */
     47static const struct pci_driver pci_driver_db __pci_driver = {
     48        .ops = &pci_ops,
     49        .vendor = PCI_VENDOR_ID_INTEL,
     50        .device = PCI_DEVICE_ID_INTEL_82801DB_PCI,
     51};
     52
     53/* 82801DBM/DBL */
     54static const struct pci_driver pci_driver_dbm __pci_driver = {
     55        .ops = &pci_ops,
    3056        .vendor = PCI_VENDOR_ID_INTEL,
    3157        .device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,
    3258};
    33 
  • trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ronald G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or modify
     7 * it under the terms of the GNU General Public License as published by
     8 * the Free Software Foundation; version 2 of the License.
     9 *
     10 * This program is distributed in the hope that it will be useful,
     11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     13 * GNU General Public License for more details.
     14 *
     15 * You should have received a copy of the GNU General Public License
     16 * along with this program; if not, write to the Free Software
     17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
     18 */
     19
    120#include <arch/io.h>
    221
    322void hard_reset(void)
    423{
    5         /* Try rebooting through port 0xcf9 */
    6         outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
     24        /* Try rebooting through port 0xcf9 */
     25        outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
    726}
  • trunk/src/southbridge/intel/i82801dx/i82801dx_smbus.c

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ronald G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or modify
     7 * it under the terms of the GNU General Public License as published by
     8 * the Free Software Foundation; version 2 of the License.
     9 *
     10 * This program is distributed in the hope that it will be useful,
     11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     13 * GNU General Public License for more details.
     14 *
     15 * You should have received a copy of the GNU General Public License
     16 * along with this program; if not, write to the Free Software
     17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
     18 */
     19
    120#include "i82801dx.h"
    221#include <smbus.h>
     
    726#define PM_DEVFN PCI_DEVFN(0x1f,3)
    827
    9 #if 0
    10 #define SMBUS_IO_BASE 0x1000
    11 #define SMBHSTSTAT 0
    12 #define SMBHSTCTL  2
    13 #define SMBHSTCMD  3
    14 #define SMBHSTADD  4
    15 #define SMBHSTDAT0 5
    16 #define SMBHSTDAT1 6
    17 #define SMBBLKDAT  7
    18 #endif
    19 
    2028void smbus_enable(void)
    2129{
     
    2432        pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1);
    2533        /* smbus enable */
    26         pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40,  1);
     34        pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1);
    2735        /* iospace enable */
    2836        pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
    2937
    30         /* Disable interrupt generation */
    31         outb(0, SMBUS_IO_BASE + SMBHSTCTL);
     38        /* Disable interrupt generation */
     39        outb(0, SMBUS_IO_BASE + SMBHSTCTL);
    3240
    3341}
     
    4048static void smbus_wait_until_ready(void)
    4149{
    42         while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
     50        while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
    4351                /* nop */
    4452        }
     
    5159                byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
    5260        }
    53         while((byte &1) == 1);
    54         while( (byte & ~1) == 0) {
     61        while ((byte & 1) == 1);
     62        while ((byte & ~1) == 0) {
    5563                byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
    5664        }
     
    7280        outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
    7381        /* set up for a byte data read */
    74         outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
     82        outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
     83             SMBUS_IO_BASE + SMBHSTCTL);
    7584
    7685        /* clear any lingering errors, so the transaction will run */
    7786        outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
    7887
    79         /* clear the data byte...*/
     88        /* clear the data byte... */
    8089        outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
    8190
    8291        /* start the command */
    83         outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
     92        outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
     93             SMBUS_IO_BASE + SMBHSTCTL);
    8494
    8595        /* poll for transaction completion */
  • trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c

    r5177 r5207  
    44 * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
    55 *
    6  * This program is free software; you can redistribute it and/or modify
    7  * it under the terms of the GNU General Public License version 2 as
    8  * published by the Free Software Foundation.
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
    910 *
    1011 * This program is distributed in the hope that it will be useful,
     
    1516 * You should have received a copy of the GNU General Public License
    1617 * along with this program; if not, write to the Free Software
    17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
    18  *
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
     19 * MA 02110-1301 USA
    1920 */
    2021
     
    3435
    3536        /* Halt the TCO timer, preventing SMI and automatic reboot */
    36         outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
     37        outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11),
     38             PMBASE_ADDR + TCOBASE + TCO1_CNT);
    3739}
  • trunk/src/southbridge/intel/i82801dx/i82801dx_usb.c

    r5167 r5207  
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2004 Ronald G. Minnich
     5 *
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, write to the Free Software
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
     19 * MA 02110-1301 USA
     20 */
     21
    122#include <console/console.h>
    223#include <device/device.h>
     
    829static void usb_init(struct device *dev)
    930{
    10 
    11 
    12 #if 0
    13         uint32_t cmd;
     31        u32 cmd;
    1432        printk_debug("USB: Setting up controller.. ");
    1533        cmd = pci_read_config32(dev, PCI_COMMAND);
    16         pci_write_config32(dev, PCI_COMMAND,
    17                 cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
    18                 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
    19 
    20 
     34        pci_write_config32(dev, PCI_COMMAND,
     35                           cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
     36                           PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
    2137        printk_debug("done.\n");
    22 #endif
    23 
    2438}
    2539
    26 static struct device_operations usb_ops  = {
    27         .read_resources   = pci_dev_read_resources,
    28         .set_resources    = pci_dev_set_resources,
     40static struct device_operations usb_ops = {
     41        .read_resources = pci_dev_read_resources,
     42        .set_resources = pci_dev_set_resources,
    2943        .enable_resources = pci_dev_enable_resources,
    30         .init             = usb_init,
    31         .scan_bus         = 0,
    32         .enable           = i82801dx_enable,
     44        .init = usb_init,
     45        .scan_bus = 0,
     46        .enable = i82801dx_enable,
    3347};
    3448
     49/* 82801DB/DBL/DBM USB1 */
    3550static const struct pci_driver usb_driver_1 __pci_driver = {
    36         .ops    = &usb_ops,
     51        .ops = &usb_ops,
    3752        .vendor = PCI_VENDOR_ID_INTEL,
    38         .device = PCI_DEVICE_ID_INTEL_82801DBM_USB1,
     53        .device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
    3954};
     55
     56/* 82801DB/DBL/DBM USB2 */
    4057static const struct pci_driver usb_driver_2 __pci_driver = {
    41         .ops    = &usb_ops,
    42         .vendor = PCI_VENDOR_ID_INTEL,
    43         .device = PCI_DEVICE_ID_INTEL_82801DBM_USB2,
     58        .ops = &usb_ops,
     59        .vendor = PCI_VENDOR_ID_INTEL,
     60        .device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
    4461};
     62
     63/* 82801DB/DBL/DBM USB3 */
    4564static const struct pci_driver usb_driver_3 __pci_driver = {
    46         .ops    = &usb_ops,
    47         .vendor = PCI_VENDOR_ID_INTEL,
    48         .device = PCI_DEVICE_ID_INTEL_82801DBM_USB3,
     65        .ops = &usb_ops,
     66        .vendor = PCI_VENDOR_ID_INTEL,
     67        .device = PCI_DEVICE_ID_INTEL_82801DB_USB3,
    4968};
  • trunk/src/southbridge/intel/i82801dx/i82801dx_usb2.c

    r5167 r5207  
    1 //2003 Copywright Tyan
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2003 Tyan
     5 *
     6 * This program is free software; you can redistribute it and/or
     7 * modify it under the terms of the GNU General Public License as
     8 * published by the Free Software Foundation; version 2 of
     9 * the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, write to the Free Software
     18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
     19 * MA 02110-1301 USA
     20 */
    221
    322#include <console/console.h>
     
    1029static void usb2_init(struct device *dev)
    1130{
    12 
    13 
    14 #if 0 
    15   uint32_t cmd;
     31        u32 cmd;
    1632        printk_debug("USB: Setting up controller.. ");
    1733        cmd = pci_read_config32(dev, PCI_COMMAND);
    18         pci_write_config32(dev, PCI_COMMAND,
    19                 cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
    20                 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
    21 
    22 
     34        pci_write_config32(dev, PCI_COMMAND,
     35                           cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
     36                           PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
    2337        printk_debug("done.\n");
    24 #endif
    2538}
    2639
    27 static struct device_operations usb2_ops  = {
    28         .read_resources   = pci_dev_read_resources,
    29         .set_resources    = pci_dev_set_resources,
     40static struct device_operations usb2_ops = {
     41        .read_resources = pci_dev_read_resources,
     42        .set_resources = pci_dev_set_resources,
    3043        .enable_resources = pci_dev_enable_resources,
    31         .init             = usb2_init,
    32         .scan_bus         = 0,
    33         .enable           = i82801dx_enable,
     44        .init = usb2_init,
     45        .scan_bus = 0,
     46        .enable = i82801dx_enable,
    3447};
    3548
     49/* 82801DB/DBM USB 2.0 */
    3650static const struct pci_driver usb2_driver __pci_driver = {
    37         .ops    = &usb2_ops,
     51        .ops = &usb2_ops,
    3852        .vendor = PCI_VENDOR_ID_INTEL,
    39         .device = PCI_DEVICE_ID_INTEL_82801DBM_EHCI,
     53        .device = PCI_DEVICE_ID_INTEL_82801DB_EHCI,
    4054};
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