Changeset 5202

Timestamp:

Mar 11, 2010 11:12:10 PM (3 years ago)

Author:

myles

Message:

Replace spaces with tabs. Trivial.

Signed-off-by: Myles Watson <mylesgw@…>
Acked-by: Myles Watson <mylesgw@…>

Location:

trunk/src/cpu/amd/car

Files:

• cache_as_ram.inc (modified) (1 diff)
• disable_cache_as_ram.c (modified) (1 diff)
• post_cache_as_ram.c (modified) (4 diffs)

trunk/src/cpu/amd/car/cache_as_ram.inc

@@ -271 +271 @@
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
-       movl    $REAL_XIP_ROM_BASE, %eax
-       orl     $MTRR_TYPE_WRBACK, %eax
+        movl    $REAL_XIP_ROM_BASE, %eax
+        orl     $MTRR_TYPE_WRBACK, %eax
         wrmsr
 

trunk/src/cpu/amd/car/disable_cache_as_ram.c

@@ -3 +3 @@
 static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
 {
-        __asm__ __volatile__ (
-        /* We don't need cache as ram for now on */
-        /* disable cache */
-        "movl    %%cr0, %%eax\n\t"
-        "orl    $(0x1<<30),%%eax\n\t"
-        "movl    %%eax, %%cr0\n\t"
+        __asm__ __volatile__ (
+        /* We don't need cache as ram for now on */
+        /* disable cache */
+        "movl    %%cr0, %%eax\n\t"
+        "orl    $(0x1<<30),%%eax\n\t"
+        "movl    %%eax, %%cr0\n\t"
 
-        /* clear sth */
-        "movl    $0x269, %%ecx\n\t"  /* fix4k_c8000*/
-        "xorl    %%edx, %%edx\n\t"
-        "xorl    %%eax, %%eax\n\t"
+        /* clear sth */
+        "movl    $0x269, %%ecx\n\t"  /* fix4k_c8000*/
+        "xorl    %%edx, %%edx\n\t"
+        "xorl    %%eax, %%eax\n\t"
         "wrmsr\n\t"
 #if CONFIG_DCACHE_RAM_SIZE > 0x8000
         "movl    $0x268, %%ecx\n\t"  /* fix4k_c0000*/
-        "wrmsr\n\t"
+        "wrmsr\n\t"
 #endif
 
-        /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
-        "movl    $0xC0010010, %%ecx\n\t"
-//        "movl    $SYSCFG_MSR, %ecx\n\t"
-        "rdmsr\n\t"
-        "andl    $(~(3<<18)), %%eax\n\t"
-//        "andl    $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
-        "wrmsr\n\t"
+        /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
+        "movl    $0xC0010010, %%ecx\n\t"
+//      "movl    $SYSCFG_MSR, %ecx\n\t"
+        "rdmsr\n\t"
+        "andl    $(~(3<<18)), %%eax\n\t"
+//      "andl    $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
+        "wrmsr\n\t"
 
-        /* Set the default memory type and disable fixed and enable variable MTRRs */
-        "movl    $0x2ff, %%ecx\n\t"
-//        "movl    $MTRRdefType_MSR, %ecx\n\t"
-        "xorl    %%edx, %%edx\n\t"
-        /* Enable Variable and Disable Fixed MTRRs */
-        "movl    $0x00000800, %%eax\n\t"
-        "wrmsr\n\t"
+        /* Set the default memory type and disable fixed and enable variable MTRRs */
+        "movl    $0x2ff, %%ecx\n\t"
+//      "movl    $MTRRdefType_MSR, %ecx\n\t"
+        "xorl    %%edx, %%edx\n\t"
+        /* Enable Variable and Disable Fixed MTRRs */
+        "movl    $0x00000800, %%eax\n\t"
+        "wrmsr\n\t"
 
-        /* enable cache */
-        "movl    %%cr0, %%eax\n\t"
-        "andl    $0x9fffffff,%%eax\n\t"
-        "movl    %%eax, %%cr0\n\t"
-        ::: "memory", "eax", "ecx", "edx"
-        );
+        /* enable cache */
+        "movl    %%cr0, %%eax\n\t"
+        "andl    $0x9fffffff,%%eax\n\t"
+        "movl    %%eax, %%cr0\n\t"
+        ::: "memory", "eax", "ecx", "edx"
+        );
 }
 

trunk/src/cpu/amd/car/post_cache_as_ram.c

@@ -6 +6 @@
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
-        printk_debug("%s%08x\r\n", strval, val);
+        printk_debug("%s%08x\r\n", strval, val);
 }
 
@@ -42 +42 @@
 
 #if 1
-        {
-        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
-        unsigned v_esp;
-        __asm__ volatile (
-                "movl   %%esp, %0\n\t"
-                : "=a" (v_esp)
-        );
-        print_debug_pcar("v_esp=", v_esp);
-        }
+        {
+        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+        unsigned v_esp;
+        __asm__ volatile (
+                "movl   %%esp, %0\n\t"
+                : "=a" (v_esp)
+        );
+        print_debug_pcar("v_esp=", v_esp);
+        }
 #endif
 
@@ -60 +60 @@
          */
 #if CONFIG_RAMTOP <= 0x100000
-        #error "You need to set CONFIG_RAMTOP greater than 1M"
+        #error "You need to set CONFIG_RAMTOP greater than 1M"
 #endif
         
@@ -72 +72 @@
         vErrata343();
 
-        memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
-//        dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
+        memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
+//      dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
-        __asm__ volatile (
-                /* set new esp */ /* before CONFIG_RAMBASE */
-                "subl   %0, %%esp\n\t"
-                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
+        __asm__ volatile (
+                /* set new esp */ /* before CONFIG_RAMBASE */
+                "subl   %0, %%esp\n\t"
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
                 /* discard all registers (eax is used for %0), so gcc redo everything
                    after the stack is moved */
                 : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
-        );
+        );
 
         /* We can put data to stack again */
 
-        /* only global variable sysinfo in cache need to be offset */
-        print_debug("Done\r\n");
-        print_debug_pcar("testx = ", testx);
+        /* only global variable sysinfo in cache need to be offset */
+        print_debug("Done\r\n");
+        print_debug_pcar("testx = ", testx);
 
         print_debug("Disabling cache as ram now \r\n");
         disable_cache_as_ram_bsp();  
 
-        print_debug("Clearing initial memory region: ");
+        print_debug("Clearing initial memory region: ");
 #if CONFIG_HAVE_ACPI_RESUME == 1
         /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
         memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
 #else
-        memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
+        memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
 #endif
-        print_debug("Done\r\n");
+        print_debug("Done\r\n");
 
 //      dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
 
-        set_sysinfo_in_ram(1); // So other core0 could start to train mem
+        set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
 #if CONFIG_MEM_TRAIN_SEQ == 1
 //      struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-        // wait for ap memory to trained
-//        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
+        // wait for ap memory to trained
+//      wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
 #endif
-        /*copy and execute coreboot_ram */
-        copy_and_run();
-        /* We will not return */
+        /*copy and execute coreboot_ram */
+        copy_and_run();
+        /* We will not return */
 
-        print_debug("should not be here -\r\n");
-
+        print_debug("should not be here -\r\n");
 }
-