Changeset 5202


Ignore:
Timestamp:
Mar 11, 2010, 10:12:10 PM (5 years ago)
Author:
myles
Message:

Replace spaces with tabs. Trivial.

Signed-off-by: Myles Watson <mylesgw@…>
Acked-by: Myles Watson <mylesgw@…>

Location:
trunk/src/cpu/amd/car
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/cpu/amd/car/cache_as_ram.inc

    r4999 r5202  
    271271#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
    272272#endif
    273        movl    $REAL_XIP_ROM_BASE, %eax
    274        orl     $MTRR_TYPE_WRBACK, %eax
     273        movl    $REAL_XIP_ROM_BASE, %eax
     274        orl     $MTRR_TYPE_WRBACK, %eax
    275275        wrmsr
    276276
  • trunk/src/cpu/amd/car/disable_cache_as_ram.c

    r5153 r5202  
    33static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
    44{
    5         __asm__ __volatile__ (
    6         /* We don't need cache as ram for now on */
    7         /* disable cache */
    8         "movl    %%cr0, %%eax\n\t"
    9         "orl    $(0x1<<30),%%eax\n\t"
    10         "movl    %%eax, %%cr0\n\t"
     5        __asm__ __volatile__ (
     6        /* We don't need cache as ram for now on */
     7        /* disable cache */
     8        "movl    %%cr0, %%eax\n\t"
     9        "orl    $(0x1<<30),%%eax\n\t"
     10        "movl    %%eax, %%cr0\n\t"
    1111
    12         /* clear sth */
    13         "movl    $0x269, %%ecx\n\t"  /* fix4k_c8000*/
    14         "xorl    %%edx, %%edx\n\t"
    15         "xorl    %%eax, %%eax\n\t"
     12        /* clear sth */
     13        "movl    $0x269, %%ecx\n\t"  /* fix4k_c8000*/
     14        "xorl    %%edx, %%edx\n\t"
     15        "xorl    %%eax, %%eax\n\t"
    1616        "wrmsr\n\t"
    1717#if CONFIG_DCACHE_RAM_SIZE > 0x8000
    1818        "movl    $0x268, %%ecx\n\t"  /* fix4k_c0000*/
    19         "wrmsr\n\t"
     19        "wrmsr\n\t"
    2020#endif
    2121
    22         /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
    23         "movl    $0xC0010010, %%ecx\n\t"
    24 //        "movl    $SYSCFG_MSR, %ecx\n\t"
    25         "rdmsr\n\t"
    26         "andl    $(~(3<<18)), %%eax\n\t"
    27 //        "andl    $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
    28         "wrmsr\n\t"
     22        /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
     23        "movl    $0xC0010010, %%ecx\n\t"
     24//      "movl    $SYSCFG_MSR, %ecx\n\t"
     25        "rdmsr\n\t"
     26        "andl    $(~(3<<18)), %%eax\n\t"
     27//      "andl    $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
     28        "wrmsr\n\t"
    2929
    30         /* Set the default memory type and disable fixed and enable variable MTRRs */
    31         "movl    $0x2ff, %%ecx\n\t"
    32 //        "movl    $MTRRdefType_MSR, %ecx\n\t"
    33         "xorl    %%edx, %%edx\n\t"
    34         /* Enable Variable and Disable Fixed MTRRs */
    35         "movl    $0x00000800, %%eax\n\t"
    36         "wrmsr\n\t"
     30        /* Set the default memory type and disable fixed and enable variable MTRRs */
     31        "movl    $0x2ff, %%ecx\n\t"
     32//      "movl    $MTRRdefType_MSR, %ecx\n\t"
     33        "xorl    %%edx, %%edx\n\t"
     34        /* Enable Variable and Disable Fixed MTRRs */
     35        "movl    $0x00000800, %%eax\n\t"
     36        "wrmsr\n\t"
    3737
    38         /* enable cache */
    39         "movl    %%cr0, %%eax\n\t"
    40         "andl    $0x9fffffff,%%eax\n\t"
    41         "movl    %%eax, %%cr0\n\t"
    42         ::: "memory", "eax", "ecx", "edx"
    43         );
     38        /* enable cache */
     39        "movl    %%cr0, %%eax\n\t"
     40        "andl    $0x9fffffff,%%eax\n\t"
     41        "movl    %%eax, %%cr0\n\t"
     42        ::: "memory", "eax", "ecx", "edx"
     43        );
    4444}
    4545
  • trunk/src/cpu/amd/car/post_cache_as_ram.c

    r5201 r5202  
    66static inline void print_debug_pcar(const char *strval, uint32_t val)
    77{
    8         printk_debug("%s%08x\r\n", strval, val);
     8        printk_debug("%s%08x\r\n", strval, val);
    99}
    1010
     
    4242
    4343#if 1
    44         {
    45         /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
    46         unsigned v_esp;
    47         __asm__ volatile (
    48                 "movl   %%esp, %0\n\t"
    49                 : "=a" (v_esp)
    50         );
    51         print_debug_pcar("v_esp=", v_esp);
    52         }
     44        {
     45        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
     46        unsigned v_esp;
     47        __asm__ volatile (
     48                "movl   %%esp, %0\n\t"
     49                : "=a" (v_esp)
     50        );
     51        print_debug_pcar("v_esp=", v_esp);
     52        }
    5353#endif
    5454
     
    6060         */
    6161#if CONFIG_RAMTOP <= 0x100000
    62         #error "You need to set CONFIG_RAMTOP greater than 1M"
     62        #error "You need to set CONFIG_RAMTOP greater than 1M"
    6363#endif
    6464       
     
    7272        vErrata343();
    7373
    74         memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
    75 //        dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
     74        memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
     75//      dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
    7676
    77         __asm__ volatile (
    78                 /* set new esp */ /* before CONFIG_RAMBASE */
    79                 "subl   %0, %%esp\n\t"
    80                 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
     77        __asm__ volatile (
     78                /* set new esp */ /* before CONFIG_RAMBASE */
     79                "subl   %0, %%esp\n\t"
     80                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
    8181                /* discard all registers (eax is used for %0), so gcc redo everything
    8282                   after the stack is moved */
    8383                : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
    84         );
     84        );
    8585
    8686        /* We can put data to stack again */
    8787
    88         /* only global variable sysinfo in cache need to be offset */
    89         print_debug("Done\r\n");
    90         print_debug_pcar("testx = ", testx);
     88        /* only global variable sysinfo in cache need to be offset */
     89        print_debug("Done\r\n");
     90        print_debug_pcar("testx = ", testx);
    9191
    9292        print_debug("Disabling cache as ram now \r\n");
    9393        disable_cache_as_ram_bsp(); 
    9494
    95         print_debug("Clearing initial memory region: ");
     95        print_debug("Clearing initial memory region: ");
    9696#if CONFIG_HAVE_ACPI_RESUME == 1
    9797        /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
    9898        memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
    9999#else
    100         memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
     100        memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
    101101#endif
    102         print_debug("Done\r\n");
     102        print_debug("Done\r\n");
    103103
    104104//      dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
    105105
    106         set_sysinfo_in_ram(1); // So other core0 could start to train mem
     106        set_sysinfo_in_ram(1); // So other core0 could start to train mem
    107107
    108108#if CONFIG_MEM_TRAIN_SEQ == 1
    109109//      struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
    110110
    111         // wait for ap memory to trained
    112 //        wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
     111        // wait for ap memory to trained
     112//      wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
    113113#endif
    114         /*copy and execute coreboot_ram */
    115         copy_and_run();
    116         /* We will not return */
     114        /*copy and execute coreboot_ram */
     115        copy_and_run();
     116        /* We will not return */
    117117
    118         print_debug("should not be here -\r\n");
    119 
     118        print_debug("should not be here -\r\n");
    120119}
    121 
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