Changeset 5201


Ignore:
Timestamp:
Mar 11, 2010, 9:34:27 PM (5 years ago)
Author:
myles
Message:

Replace clear_memory with memset.
Replace set_init_ram_access with the call to set_var_mtrr.
Remove unused #include statments.

Signed-off-by: Myles Watson <mylesgw@…>
Acked-by: Patrick Georgi <patrick.georgi@…>

Location:
trunk/src
Files:
2 deleted
17 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/cpu/amd/car/post_cache_as_ram.c

    r5153 r5201  
    33 */
    44#include "cpu/amd/car/disable_cache_as_ram.c"
    5 
    6 #include "cpu/amd/car/clear_init_ram.c"
    75
    86static inline void print_debug_pcar(const char *strval, uint32_t val)
     
    6563#endif
    6664       
    67         set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
     65        /* So we can access RAM from [1M, CONFIG_RAMTOP) */
     66        set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
    6867
    6968//      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
     
    9594
    9695        print_debug("Clearing initial memory region: ");
    97         clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
     96#if CONFIG_HAVE_ACPI_RESUME == 1
     97        /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
     98        memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
     99#else
     100        memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
     101#endif
    98102        print_debug("Done\r\n");
    99103
  • trunk/src/cpu/amd/model_10xxx/init_cpus.c

    r5092 r5201  
    422422                //wait_till_sysinfo_in_ram();
    423423
    424                 set_init_ram_access();
     424                set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
    425425
    426426                STOP_CAR_AND_CPU();
  • trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c

    r5200 r5201  
    3535#include <cpu/x86/cache.h>
    3636#include <cpu/x86/mtrr.h>
    37 #include <cpu/x86/mem.h>
    3837#include <cpu/amd/quadcore.h>
    3938#include <cpu/amd/model_10xxx_msr.h>
  • trunk/src/cpu/amd/model_fxx/init_cpus.c

    r4856 r5201  
    318318                        }
    319319                        lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
    320                         set_init_ram_access();
     320                        set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
    321321        #if CONFIG_MEM_TRAIN_SEQ == 1
    322322                        train_ram_on_node(id.nodeid, id.coreid, sysinfo,
  • trunk/src/cpu/amd/model_fxx/model_fxx_init.c

    r4890 r5201  
    2525#include <cpu/x86/cache.h>
    2626#include <cpu/x86/mtrr.h>
    27 #include <cpu/x86/mem.h>
    2827
    2928#include <cpu/amd/dualcore.h>
     
    239238                /* clear memory 2M (limitk - basek) */
    240239                addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
    241                 clear_memory(addr, size);
     240                memset(addr, size, 0);
    242241}
    243242
  • trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

    r5185 r5201  
    131131#include "northbridge/amd/amdht/ht_wrapper.c"
    132132
    133 #include "include/cpu/x86/mem.h"
    134133#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
    135134#include "northbridge/amd/amdfam10/raminit_amdmct.c"
  • trunk/src/mainboard/msi/ms9652_fam10/romstage.c

    r5184 r5201  
    111111#include "northbridge/amd/amdht/ht_wrapper.c"
    112112
    113 #include "include/cpu/x86/mem.h"
    114113#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
    115114#include "northbridge/amd/amdfam10/raminit_amdmct.c"
  • trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c

    r5092 r5201  
    109109#include "northbridge/amd/amdht/ht_wrapper.c"
    110110
    111 #include "include/cpu/x86/mem.h"
    112111#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
    113112#include "northbridge/amd/amdfam10/raminit_amdmct.c"
  • trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c

    r5154 r5201  
    109109#include "northbridge/amd/amdht/ht_wrapper.c"
    110110
    111 #include "include/cpu/x86/mem.h"
    112111#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
    113112#include "northbridge/amd/amdfam10/raminit_amdmct.c"
  • trunk/src/mainboard/tyan/s2912_fam10/romstage.c

    r5184 r5201  
    111111#include "northbridge/amd/amdht/ht_wrapper.c"
    112112
    113 #include "include/cpu/x86/mem.h"
    114113#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
    115114#include "northbridge/amd/amdfam10/raminit_amdmct.c"
  • trunk/src/northbridge/amd/amdk8/raminit.c

    r4890 r5201  
    55*/
    66
    7 #include <cpu/x86/mem.h>
    87#include <cpu/x86/cache.h>
    98#include <cpu/x86/mtrr.h>
  • trunk/src/northbridge/amd/amdk8/raminit_f.c

    r5185 r5201  
    2121*/
    2222
    23 #include <cpu/x86/mem.h>
    2423#include <cpu/x86/cache.h>
    2524#include <cpu/x86/mtrr.h>
  • trunk/src/northbridge/intel/e7520/raminit.c

    r3624 r5201  
    1919 */
    2020
    21 #include <cpu/x86/mem.h>
    2221#include <cpu/x86/mtrr.h>
    2322#include <cpu/x86/cache.h>
  • trunk/src/northbridge/intel/e7525/raminit.c

    r3624 r5201  
    1919 */
    2020
    21 #include <cpu/x86/mem.h>
    2221#include <cpu/x86/mtrr.h>
    2322#include <cpu/x86/cache.h>
  • trunk/src/northbridge/intel/i3100/raminit.c

    r4392 r5201  
    2020 */
    2121
    22 #include <cpu/x86/mem.h>
    2322#include <cpu/x86/mtrr.h>
    2423#include <cpu/x86/cache.h>
  • trunk/src/northbridge/intel/i3100/raminit_ep80579.c

    r4615 r5201  
    2020 */
    2121
    22 #include <cpu/x86/mem.h>
    2322#include <cpu/x86/mtrr.h>
    2423#include <cpu/x86/cache.h>
  • trunk/src/northbridge/intel/i945/raminit.c

    r5190 r5201  
    1818 */
    1919
    20 #include <cpu/x86/mem.h>
    2120#include <cpu/x86/mtrr.h>
    2221#include <cpu/x86/cache.h>
Note: See TracChangeset for help on using the changeset viewer.