Changeset 5155


Ignore:
Timestamp:
Feb 24, 2010, 2:09:09 PM (5 years ago)
Author:
stepan
Message:

Remove register pressure from e7501 driver by not indirectly referencing
0:0.0 through a struct passed all through the code. This behavior makes a lot
of sense for CPUs with a memory controller built-in. But this is not the case
for the e7501.

Signed-off-by: Stefan Reinauer <stepan@…>
Acked-by: Ronald G. Minnich <rminnich@…>
Acked-by: Uwe Hermann <uwe@…>

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/northbridge/intel/e7501/raminit.c

    r3624 r5155  
    808808//----------------------------------------------------------------------------------
    809809// Function:            do_ram_command
    810 // Parameters:          ctrl - PCI addresses of memory controller functions, and
    811 //                                              SMBus addresses of DIMM slots on the mainboard
     810// Parameters:         
    812811//                                      command - specifies the command to be sent to the DIMMs:
    813812//                                              RAM_COMMAND_NOP                 - No Operation
     
    822821// Description:         Send the specified command to all DIMMs.
    823822//
    824 static void do_ram_command(const struct mem_controller *ctrl, uint8_t command,
    825                                                    uint16_t jedec_mode_bits)
     823static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
    826824{
    827825    int i;
     
    831829
    832830        // Configure the RAM command
    833     dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
     831    dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
    834832    dram_controller_mode &= 0xFFFFFF8F;
    835833    dram_controller_mode |= command;
    836     pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
     834    pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
    837835
    838836        // RAM_COMMAND_NORMAL is an exception.
     
    866864                for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
    867865
    868                         uint8_t dimm_end_64M_multiple = pci_read_config8(ctrl->d0, DRB_ROW_0 + i);
     866                        uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
    869867                        if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
    870868
     
    891889//----------------------------------------------------------------------------------
    892890// Function:            set_ram_mode
    893 // Parameters:          ctrl - PCI addresses of memory controller functions, and
    894 //                                              SMBus addresses of DIMM slots on the mainboard
    895 //                                      jedec_mode_bits - for mode register set & extended mode register set
    896 //                                              commands, bits 0-12 contain the register value in JEDEC format.
     891// Parameters:          jedec_mode_bits - for mode register set & extended mode register set
     892//                      commands, bits 0-12 contain the register value in JEDEC format.
    897893// Return Value:        None
    898894// Description:         Set the mode register of all DIMMs. The proper CAS# latency
    899895//                                      setting is added to the mode bits specified by the caller.
    900896//
    901 static void set_ram_mode(const struct mem_controller *ctrl, uint16_t jedec_mode_bits)
     897static void set_ram_mode(uint16_t jedec_mode_bits)
    902898{
    903899        ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
    904900
    905         uint32_t dram_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK;
     901        uint32_t dram_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
    906902       
    907903        switch (dram_cas_latency) {
     
    919915        }
    920916
    921         do_ram_command(ctrl, RAM_COMMAND_MRS, jedec_mode_bits);
     917        do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
    922918}
    923919
     
    928924//----------------------------------------------------------------------------------
    929925// Function:            configure_dimm_row_boundaries
    930 // Parameters:          ctrl - PCI addresses of memory controller functions, and
    931 //                                              SMBus addresses of DIMM slots on the mainboard
     926// Parameters:         
    932927//                                      dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
    933928//                                      total_dram_64M_multiple - total DRAM in the system (as a
     
    939934//                                      present in the specified DIMM.
    940935//
    941 static uint8_t configure_dimm_row_boundaries(const struct mem_controller *ctrl,
     936static uint8_t configure_dimm_row_boundaries(
    942937                                                                                         struct dimm_size dimm_log2_num_bits,
    943938                                                                                         uint8_t total_dram_64M_multiple,
     
    968963
    969964        // Configure the boundary address for the row on side 1
    970         pci_write_config8(ctrl->d0, DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple);
     965        pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple);
    971966
    972967        // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
     
    976971       
    977972        // Configure the boundary address for the row (if any) on side 2
    978     pci_write_config8(ctrl->d0, DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple);
     973    pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple);
    979974
    980975        // Update boundaries for rows subsequent to these.
     
    982977       
    983978    for(i=dimm_index+1; i<MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
    984                 pci_write_config8(ctrl->d0, DRB_ROW_0+(i<<1), total_dram_64M_multiple);
    985         pci_write_config8(ctrl->d0, DRB_ROW_1+(i<<1), total_dram_64M_multiple);
     979                pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(i<<1), total_dram_64M_multiple);
     980        pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(i<<1), total_dram_64M_multiple);
    986981        }
    987982       
     
    10091004        // Configure the E7501's DRAM row boundaries
    10101005        // Start by zeroing out the temporary initial configuration
    1011         pci_write_config32(ctrl->d0, DRB_ROW_0, 0);
    1012         pci_write_config32(ctrl->d0, DRB_ROW_4, 0);
     1006        pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0);
     1007        pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0);
    10131008
    10141009        for(i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
     
    10311026                        die("Bad SPD value\r\n");
    10321027
    1033                 total_dram_64M_multiple = configure_dimm_row_boundaries(ctrl, sz, total_dram_64M_multiple, i);
     1028                total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
    10341029        }
    10351030
     
    10651060                uint16_t top_of_low_memory = total_dram_128M_multiple << 11;
    10661061
    1067         pci_write_config16(ctrl->d0, TOLM, top_of_low_memory);
     1062        pci_write_config16(PCI_DEV(0, 0, 0), TOLM, top_of_low_memory);
    10681063
    10691064        } else {
     
    10771072                // Put TOLM at 3 GB
    10781073
    1079                 pci_write_config16(ctrl->d0, TOLM, 0xc000);
     1074                pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000);
    10801075
    10811076                // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
     
    10901085                }
    10911086
    1092         pci_write_config16(ctrl->d0, REMAPBASE, remap_base);
    1093         pci_write_config16(ctrl->d0, REMAPLIMIT, remap_limit);
     1087        pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, remap_base);
     1088        pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, remap_limit);
    10941089        }
    10951090}
     
    10971092//----------------------------------------------------------------------------------
    10981093// Function:            initialize_ecc
    1099 // Parameters:          ctrl - PCI addresses of memory controller functions, and
    1100 //                                              SMBus addresses of DIMM slots on the mainboard
     1094// Parameters:          None
    11011095// Return Value:        None
    11021096// Description:         If we're configured to use ECC, initialize the SDRAM and
    11031097//                                      clear the E7501's ECC error flags.
    11041098//
    1105 static void initialize_ecc(const struct mem_controller *ctrl)
     1099static void initialize_ecc(void)
    11061100{
    11071101        uint32_t dram_controller_mode;
    11081102
    11091103        /* Test to see if ECC support is enabled */
    1110         dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
     1104        dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
    11111105        dram_controller_mode >>= 20;
    11121106        dram_controller_mode &= 3;
     
    11171111                RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
    11181112                /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
    1119                 pci_write_config8(ctrl->d0, MCHCFGNS, 0x06);
    1120                 pci_write_config8(ctrl->d0, MCHCFGNS, 0x07);
     1113                pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
     1114                pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
    11211115
    11221116                // Wait for scrub cycle to complete
    11231117                do {
    1124                         byte = pci_read_config8(ctrl->d0, MCHCFGNS);
     1118                        byte = pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
    11251119
    11261120                } while ( (byte & 0x08 ) == 0);
    11271121
    1128                 pci_write_config8(ctrl->d0, MCHCFGNS, byte & 0xfc);
     1122                pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
    11291123                RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");       
    11301124
    11311125                /* Clear the ECC error bits */
    1132                 pci_write_config8(ctrl->d0f1, DRAM_FERR, 0x03);
    1133                 pci_write_config8(ctrl->d0f1, DRAM_NERR, 0x03);
     1126                pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
     1127                pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03);
    11341128
    11351129                // Clear DRAM Interface error bits (write-one-clear)
    1136                 pci_write_config32(ctrl->d0f1, FERR_GLOBAL, 1<<18);
    1137             pci_write_config32(ctrl->d0f1, NERR_GLOBAL, 1<<18);
     1130                pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1<<18);
     1131            pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1<<18);
    11381132
    11391133                // Start normal ECC scrub
    1140                 pci_write_config8(ctrl->d0, MCHCFGNS, 5);
     1134                pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5);
    11411135        }
    11421136       
     
    11621156        uint8_t slowest_ras_cas_delay = 0;
    11631157        uint8_t slowest_active_to_precharge_delay = 0;
    1164         uint32_t current_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK;
     1158        uint32_t current_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
    11651159
    11661160        // CAS# latency must be programmed beforehand
     
    12011195
    12021196    /* Read the initial state */
    1203     dram_timing = pci_read_config32(ctrl->d0, DRT);
     1197    dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
    12041198
    12051199        /* Trp */
     
    12611255                dram_timing |= (1<<28);         // 4 clocks
    12621256
    1263         pci_write_config32(ctrl->d0, DRT, dram_timing);
     1257        pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
    12641258
    12651259        return;
     
    13521346         */
    13531347
    1354         dram_timing = pci_read_config32(ctrl->d0, DRT);
     1348        dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
    13551349        dram_timing &= ~(DRT_CAS_MASK);
    13561350
    1357         maybe_dram_read_timing = pci_read_config16(ctrl->d0, MAYBE_DRDCTL);
     1351        maybe_dram_read_timing = pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
    13581352        maybe_dram_read_timing &= 0xF00C;
    13591353
     
    13641358        else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
    13651359
    1366                 uint32_t dram_row_attributes = pci_read_config32(ctrl->d0, DRA);
     1360                uint32_t dram_row_attributes = pci_read_config32(PCI_DEV(0, 0, 0), DRA);
    13671361
    13681362                dram_timing |= DRT_CAS_2_5;
     
    13851379                die("No CAS# latencies compatible with all DIMMs!!\r\n");
    13861380
    1387         pci_write_config32(ctrl->d0, DRT, dram_timing);
     1381        pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
    13881382
    13891383        /* set master DLL reset */
    1390         dword = pci_read_config32(ctrl->d0, 0x88);
     1384        dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
    13911385        dword |= (1<<26);
    1392         pci_write_config32(ctrl->d0, 0x88, dword);
     1386        pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
    13931387       
    13941388        dword &= 0x0c0007ff;    /* patch try register 88 is undocumented tnz */
    13951389        dword |= 0xd2109800;
    13961390
    1397         pci_write_config32(ctrl->d0, 0x88, dword);
    1398 
    1399        
    1400         pci_write_config16(ctrl->d0, MAYBE_DRDCTL, maybe_dram_read_timing);
    1401        
    1402         dword = pci_read_config32(ctrl->d0, 0x88);      /* reset master DLL reset */
     1391        pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
     1392
     1393       
     1394        pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, maybe_dram_read_timing);
     1395       
     1396        dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);      /* reset master DLL reset */
    14031397        dword &= ~(1<<26);
    1404         pci_write_config32(ctrl->d0, 0x88, dword);
     1398        pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
    14051399
    14061400        return;
     
    14271421
    14281422        // Initial settings
    1429     uint32_t controller_mode = pci_read_config32(ctrl->d0, DRC);
     1423    uint32_t controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
    14301424        uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
    14311425
     
    15081502
    15091503        // Configure the E7501
    1510         pci_write_config32(ctrl->d0, DRC, controller_mode);
     1504        pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode);
    15111505}
    15121506
     
    15631557
    15641558        /* Write the new row attributes register */
    1565         pci_write_config32(ctrl->d0, DRA, row_attributes);
     1559        pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes);
    15661560}
    15671561
    15681562//----------------------------------------------------------------------------------
    15691563// Function:            enable_e7501_clocks
    1570 // Parameters:          ctrl - PCI addresses of memory controller functions, and
    1571 //                                              SMBus addresses of DIMM slots on the mainboard
    1572 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
     1564// Parameters:          dimm_mask - bitmask of populated DIMMs on the board - see
    15731565//                                                              spd_get_supported_dimms()
    15741566// Return Value:        None
     
    15761568//                                      for unpopulated sockets (to reduce EMI).
    15771569//
    1578 static void enable_e7501_clocks(const struct mem_controller *ctrl, uint8_t dimm_mask)
     1570static void enable_e7501_clocks(uint8_t dimm_mask)
    15791571{
    15801572        int i;
    1581         uint8_t clock_disable = pci_read_config8(ctrl->d0, CKDIS);
     1573        uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
    15821574
    15831575        for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
     
    15911583        }
    15921584       
    1593         pci_write_config8(ctrl->d0, CKDIS, clock_disable);
     1585        pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
    15941586}
    15951587
     
    16061598// Description:         DDR Receive FIFO RE-Sync (?)
    16071599//
    1608 static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl)
     1600static void RAM_RESET_DDR_PTR(void)
    16091601{
    16101602        uint8_t byte;
    1611         byte = pci_read_config8(ctrl->d0, 0x88);
     1603        byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
    16121604        byte |= (1 << 4);
    1613         pci_write_config8(ctrl->d0, 0x88, byte);
    1614 
    1615         byte = pci_read_config8(ctrl->d0, 0x88);
     1605        pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
     1606
     1607        byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
    16161608        byte &= ~(1 << 4);
    1617         pci_write_config8(ctrl->d0, 0x88, byte);
     1609        pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
    16181610}
    16191611
    16201612//----------------------------------------------------------------------------------
    16211613// Function:            ram_set_d0f0_regs
    1622 // Parameters:          ctrl - PCI addresses of memory controller functions, and
    1623 //                                              SMBus addresses of DIMM slots on the mainboard
     1614// Parameters:          None
    16241615// Return Value:        None
    16251616// Description:         Set E7501 registers that are either independent of DIMM specifics,
     
    16301621//                                      configuration register offset, mask, and bits to set.
    16311622//
    1632 static void ram_set_d0f0_regs(const struct mem_controller *ctrl)
     1623static void ram_set_d0f0_regs(void)
    16331624{
    16341625        int i;
     
    16521643                ASSERT((bits_to_mask & bits_to_set) == 0);
    16531644
    1654                 register_value = pci_read_config32(ctrl->d0, register_offset);
     1645                register_value = pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
    16551646        register_value &= bits_to_mask;
    16561647        register_value |= bits_to_set;
    16571648
    1658         pci_write_config32(ctrl->d0, register_offset, register_value);
     1649        pci_write_config32(PCI_DEV(0, 0, 0), register_offset, register_value);
    16591650    }
    16601651}
     
    16791670//----------------------------------------------------------------------------------
    16801671// Function:            ram_set_rcomp_regs
    1681 // Parameters:          ctrl - PCI addresses of memory controller functions, and
    1682 //                                              SMBus addresses of DIMM slots on the mainboard
     1672// Parameters:          None
    16831673// Return Value:        None
    16841674// Description:         Set the E7501's (undocumented) RCOMP registers.
     
    16891679//                                      between the E7501 and these two chips.
    16901680//
    1691 static void ram_set_rcomp_regs(const struct mem_controller *ctrl)
     1681static void ram_set_rcomp_regs(void)
    16921682{
    16931683        uint32_t dword;
     
    16971687
    16981688        /*enable access to the rcomp bar*/
    1699         dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST);
     1689        dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
    17001690    dword |= (1<<22);
    1701     pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword);
     1691    pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
    17021692       
    17031693
    17041694        // Set the RCOMP MMIO base address
    1705     pci_write_config32(ctrl->d0, MAYBE_SMRBASE, RCOMP_MMIO);
     1695    pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
    17061696
    17071697        // Block RCOMP updates while we configure the registers
     
    17901780
    17911781        /*disable access to the rcomp bar */
    1792         dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST);
     1782        dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
    17931783        dword &= ~(1<<22);
    1794         pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword);     
     1784        pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);     
    17951785
    17961786}
     
    18121802static void sdram_enable(int controllers, const struct mem_controller *ctrl)
    18131803{
    1814         uint8_t dimm_mask = pci_read_config16(ctrl->d0, SKPD);
     1804        uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD);
    18151805        uint32_t dram_controller_mode;
    18161806
     
    18291819        /* 3. Apply NOP */
    18301820        RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
    1831         do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
     1821        do_ram_command(RAM_COMMAND_NOP, 0);
    18321822        EXTRA_DELAY
    18331823
    18341824        /* 4 Precharge all */
    18351825        RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
    1836         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
     1826        do_ram_command(RAM_COMMAND_PRECHARGE, 0);
    18371827        EXTRA_DELAY
    18381828       
     
    18401830        /* 5. Issue EMRS to enable DLL */
    18411831        RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
    1842         do_ram_command(ctrl, RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
     1832        do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
    18431833        EXTRA_DELAY
    18441834       
    18451835        /* 6. Reset DLL */
    18461836        RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
    1847         set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
     1837        set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
    18481838        EXTRA_DELAY
    18491839
     
    18571847        /* 7 Precharge all */
    18581848        RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
    1859         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
     1849        do_ram_command(RAM_COMMAND_PRECHARGE, 0);
    18601850        EXTRA_DELAY
    18611851       
    18621852        /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
    18631853        RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
    1864         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1854        do_ram_command(RAM_COMMAND_CBR, 0);
    18651855        EXTRA_DELAY
    1866         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1856        do_ram_command(RAM_COMMAND_CBR, 0);
    18671857        EXTRA_DELAY
    18681858        /* And for good luck 6 more CBRs */
    1869         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1859        do_ram_command(RAM_COMMAND_CBR, 0);
    18701860        EXTRA_DELAY
    1871         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1861        do_ram_command(RAM_COMMAND_CBR, 0);
    18721862        EXTRA_DELAY
    1873         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1863        do_ram_command(RAM_COMMAND_CBR, 0);
    18741864        EXTRA_DELAY
    1875         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1865        do_ram_command(RAM_COMMAND_CBR, 0);
    18761866        EXTRA_DELAY
    1877         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1867        do_ram_command(RAM_COMMAND_CBR, 0);
    18781868        EXTRA_DELAY
    1879         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
     1869        do_ram_command(RAM_COMMAND_CBR, 0);
    18801870        EXTRA_DELAY
    18811871
    18821872        /* 9 mode register set */
    18831873        RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
    1884         set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
     1874        set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
    18851875        EXTRA_DELAY
    18861876       
    18871877        /* 10 DDR Receive FIFO RE-Sync */
    18881878        RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
    1889         RAM_RESET_DDR_PTR(ctrl);
     1879        RAM_RESET_DDR_PTR();
    18901880        EXTRA_DELAY
    18911881       
    18921882        /* 11 normal operation */
    18931883        RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
    1894         do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
     1884        do_ram_command(RAM_COMMAND_NORMAL, 0);
    18951885        EXTRA_DELAY
    18961886
     
    19001890
    19011891    /* Finally enable refresh */
    1902         dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
     1892        dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
    19031893        dram_controller_mode |= (1 << 29);
    1904         pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
     1894        pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
    19051895        EXTRA_DELAY
    19061896
    1907         initialize_ecc(ctrl);
    1908 
    1909         dram_controller_mode = pci_read_config32(ctrl->d0, DRC); /* FCS_EN */
     1897        initialize_ecc();
     1898
     1899        dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */
    19101900        dram_controller_mode |= (1<<17);                // NOTE: undocumented reserved bit
    1911         pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
     1901        pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
    19121902
    19131903        RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
     
    19411931    } else {
    19421932
    1943                 enable_e7501_clocks(ctrl, dimm_mask);
     1933                enable_e7501_clocks(dimm_mask);
    19441934
    19451935                RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
     
    19481938                configure_e7501_dram_controller_mode(ctrl, dimm_mask);
    19491939                configure_e7501_cas_latency(ctrl, dimm_mask);
    1950                 RAM_RESET_DDR_PTR(ctrl);
     1940                RAM_RESET_DDR_PTR();
    19511941
    19521942                configure_e7501_dram_timing(ctrl, dimm_mask);
     
    19641954        //               configure_e7501_ram_addresses() without having to regenerate the bitmask
    19651955        //               of usable DIMMs.
    1966         pci_write_config16(ctrl->d0, SKPD, dimm_mask);
     1956        pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
    19671957}
    19681958
     
    19801970        DUMPNORTH();
    19811971
    1982         ram_set_rcomp_regs(ctrl);
    1983     ram_set_d0f0_regs(ctrl);
     1972        ram_set_rcomp_regs();
     1973    ram_set_d0f0_regs();
    19841974}
    19851975
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