Changeset 5154
- Timestamp:
- Feb 24, 2010 9:48:35 AM (3 years ago)
- Location:
- trunk/src/mainboard/supermicro/h8qme_fam10
- Files:
-
- 4 edited
-
Kconfig (modified) (4 diffs)
-
devicetree.cb (modified) (4 diffs)
-
mptable.c (modified) (2 diffs)
-
romstage.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
r5075 r5154 5 5 select NORTHBRIDGE_AMD_AMDFAM10 6 6 select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX 7 select SOUTHBRIDGE_AMD_AMD8132 7 8 select SOUTHBRIDGE_NVIDIA_MCP55 8 9 select SUPERIO_WINBOND_W83627HF … … 50 51 config HEAP_SIZE 51 52 hex 52 default 0x c000053 default 0xff000 53 54 depends on BOARD_SUPERMICRO_H8QME_FAM10 54 55 … … 135 136 config SERIAL_CPU_INIT 136 137 bool 137 default n138 default y 138 139 depends on BOARD_SUPERMICRO_H8QME_FAM10 139 140 … … 142 143 default 0x1511 143 144 depends on BOARD_SUPERMICRO_H8QME_FAM10 145 146 config STACK_SIZE 147 hex 148 default 0x10000 149 depends on BOARD_SUPERMICRO_H8QME_FAM10 -
trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
r5075 r5154 28 28 irq 0x70 = 4 29 29 end 30 device pnp 2e.3 on# Com230 device pnp 2e.3 off # Com2 31 31 io 0x60 = 0x2f8 32 32 irq 0x70 = 3 … … 55 55 end 56 56 end 57 device pci 1.1 on # SM 0 58 chip drivers/generic/generic #dimm 0-0-0 59 device i2c 50 on end 60 end 61 chip drivers/generic/generic #dimm 0-0-1 62 device i2c 51 on end 63 end 64 chip drivers/generic/generic #dimm 0-1-0 65 device i2c 52 on end 66 end 67 chip drivers/generic/generic #dimm 0-1-1 68 device i2c 53 on end 69 end 70 chip drivers/generic/generic #dimm 1-0-0 71 device i2c 54 on end 72 end 73 chip drivers/generic/generic #dimm 1-0-1 74 device i2c 55 on end 75 end 76 chip drivers/generic/generic #dimm 1-1-0 77 device i2c 56 on end 78 end 79 chip drivers/generic/generic #dimm 1-1-1 80 device i2c 57 on end 81 end 82 end # SM 57 device pci 1.1 on end 83 58 device pci 1.1 on # SM 1 84 59 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? 85 # chip drivers/generic/generic #PCIXA Slot1 86 # device i2c 50 on end 87 # end 88 # chip drivers/generic/generic #PCIXB Slot1 89 # device i2c 51 on end 90 # end 91 # chip drivers/generic/generic #PCIXB Slot2 92 # device i2c 52 on end 93 # end 94 # chip drivers/generic/generic #PCI Slot1 95 # device i2c 53 on end 96 # end 97 # chip drivers/generic/generic #Master MCP55 PCI-E 98 # device i2c 54 on end 99 # end 100 # chip drivers/generic/generic #Slave MCP55 PCI-E 101 # device i2c 55 on end 102 # end 60 # 103 61 chip drivers/generic/generic #MAC EEPROM 104 62 device i2c 51 on end … … 112 70 device pci 5.1 on end # SATA 1 113 71 device pci 5.2 on end # SATA 2 114 device pci 6.0 on # PCI 115 device pci 6.0 on end 72 device pci 6.1 off end # AZA 73 device pci 7.0 on 74 device pci 1.0 on end 116 75 end 117 device pci 6.1 on end # AZA 118 device pci 8.0 on end # NIC 119 device pci 9.0 on end # NIC 120 device pci a.0 on # PCI E 5 121 device pci 0.0 on #nec pci-x 122 end 123 device pci 0.1 on #nec pci-x 124 device pci 4.0 on end #scsi 125 device pci 4.1 on end #scsi 126 end 127 end 76 device pci 8.0 off end 77 device pci 9.0 off end 78 device pci a.0 on end # PCI E 5 128 79 device pci b.0 on end # PCI E 4 129 80 device pci c.0 on end # PCI E 3 … … 143 94 device pci 18.4 on end 144 95 device pci 19.0 on end 96 device pci 19.0 on end 97 device pci 19.0 on 98 chip southbridge/amd/amd8132 99 device pci 0.0 on end 100 device pci 0.1 on end 101 device pci 1.0 on 102 device pci 3.0 on end 103 device pci 3.1 on end 104 end 105 device pci 1.1 on end 106 end #amd8132 107 end #device pci 19.0 145 108 device pci 19.1 on end 146 109 device pci 19.2 on end -
trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c
r5080 r5154 95 95 96 96 dword = 0xa000000b; 97 dword = 0x10000002;98 97 pci_write_config32(dev, 0x84, dword); 99 98 100 99 } 101 100 102 /* 8132_1 */103 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,1));104 res = find_resource(dev,PCI_BASE_ADDRESS_0);105 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);106 107 /* 8132_2 */108 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,1));109 res = find_resource(dev,PCI_BASE_ADDRESS_0);110 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);111 101 112 102 } … … 126 116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); 127 117 128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus ! Not correctly assign!!*/118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ 129 119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ 130 120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ -
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
r5092 r5154 119 119 120 120 #define MCP55_NUM 1 121 #define MCP55_USE_NIC 1122 #define MCP55_USE_AZA 1121 #define MCP55_USE_NIC 0 122 #define MCP55_USE_AZA 0 123 123 124 124 #define MCP55_PCI_E_X_0 4
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