Changeset 5142
- Timestamp:
- Feb 22, 2010 12:26:06 PM (3 years ago)
- Location:
- trunk/util/inteltool
- Files:
-
- 6 edited
-
cpu.c (modified) (4 diffs)
-
inteltool.c (modified) (2 diffs)
-
inteltool.h (modified) (2 diffs)
-
memory.c (modified) (2 diffs)
-
pcie.c (modified) (3 diffs)
-
powermgt.c (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/util/inteltool/cpu.c
r4621 r5142 2 2 * inteltool - dump all registers on an Intel CPU + chipset based system. 3 3 * 4 * Copyright (C) 2008 by coresystems GmbH4 * Copyright (C) 2008-2010 by coresystems GmbH 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify … … 97 97 char *name; 98 98 } msr_entry_t; 99 100 static const msr_entry_t model6bx_global_msrs[] = { 101 { 0x0010, "IA32_TIME_STAMP_COUNTER" }, 102 { 0x0017, "IA32_PLATFORM_ID" }, 103 { 0x001b, "IA32_APIC_BASE" }, 104 { 0x002a, "EBL_CR_POWERON" }, 105 { 0x0033, "TEST_CTL" }, 106 { 0x003f, "THERM_DIODE_OFFSET" }, 107 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO 108 { 0x008b, "IA32_BIOS_SIGN_ID" }, 109 { 0x00c1, "PERFCTR0" }, 110 { 0x00c2, "PERFCTR1" }, 111 { 0x011e, "BBL_CR_CTL3" }, 112 { 0x0179, "IA32_MCG_CAP" }, 113 { 0x017a, "IA32_MCG_STATUS" }, 114 { 0x0198, "IA32_PERF_STATUS" }, 115 { 0x0199, "IA32_PERF_CONTROL" }, 116 { 0x019a, "IA32_CLOCK_MODULATION" }, 117 { 0x01a0, "IA32_MISC_ENABLES" }, 118 { 0x01d9, "IA32_DEBUGCTL" }, 119 { 0x0200, "IA32_MTRR_PHYSBASE0" }, 120 { 0x0201, "IA32_MTRR_PHYSMASK0" }, 121 { 0x0202, "IA32_MTRR_PHYSBASE1" }, 122 { 0x0203, "IA32_MTRR_PHYSMASK1" }, 123 { 0x0204, "IA32_MTRR_PHYSBASE2" }, 124 { 0x0205, "IA32_MTRR_PHYSMASK2" }, 125 { 0x0206, "IA32_MTRR_PHYSBASE3" }, 126 { 0x0207, "IA32_MTRR_PHYSMASK3" }, 127 { 0x0208, "IA32_MTRR_PHYSBASE4" }, 128 { 0x0209, "IA32_MTRR_PHYSMASK4" }, 129 { 0x020a, "IA32_MTRR_PHYSBASE5" }, 130 { 0x020b, "IA32_MTRR_PHYSMASK5" }, 131 { 0x020c, "IA32_MTRR_PHYSBASE6" }, 132 { 0x020d, "IA32_MTRR_PHYSMASK6" }, 133 { 0x020e, "IA32_MTRR_PHYSBASE7" }, 134 { 0x020f, "IA32_MTRR_PHYSMASK7" }, 135 { 0x0250, "IA32_MTRR_FIX64K_00000" }, 136 { 0x0258, "IA32_MTRR_FIX16K_80000" }, 137 { 0x0259, "IA32_MTRR_FIX16K_A0000" }, 138 { 0x0268, "IA32_MTRR_FIX4K_C0000" }, 139 { 0x0269, "IA32_MTRR_FIX4K_C8000" }, 140 { 0x026a, "IA32_MTRR_FIX4K_D0000" }, 141 { 0x026b, "IA32_MTRR_FIX4K_D8000" }, 142 { 0x026c, "IA32_MTRR_FIX4K_E0000" }, 143 { 0x026d, "IA32_MTRR_FIX4K_E8000" }, 144 { 0x026e, "IA32_MTRR_FIX4K_F0000" }, 145 { 0x026f, "IA32_MTRR_FIX4K_F8000" }, 146 { 0x02ff, "IA32_MTRR_DEF_TYPE" }, 147 { 0x0400, "IA32_MC0_CTL" }, 148 { 0x0401, "IA32_MC0_STATUS" }, 149 { 0x0402, "IA32_MC0_ADDR" }, 150 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO 151 { 0x040c, "IA32_MC4_CTL" }, 152 { 0x040d, "IA32_MC4_STATUS" }, 153 { 0x040e, "IA32_MC4_ADDR" }, 154 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO 155 }; 156 157 static const msr_entry_t model6bx_per_core_msrs[] = { 158 // single core only 159 }; 99 160 100 161 static const msr_entry_t model6ex_global_msrs[] = { … … 260 321 261 322 cpu_t cpulist[] = { 323 { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, 262 324 { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, 263 325 { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, … … 316 378 break; 317 379 #endif 318 printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); 380 if (cpu->num_per_core_msrs) 381 printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); 319 382 320 383 for (i = 0; i < cpu->num_per_core_msrs; i++) { -
trunk/util/inteltool/inteltool.c
r4905 r5142 2 2 * inteltool - dump all registers on an Intel CPU + chipset based system. 3 3 * 4 * Copyright (C) 2008 by coresystems GmbH4 * Copyright (C) 2008-2010 by coresystems GmbH 5 5 * written by Stefan Reinauer <stepan@coresystems.de> 6 6 * … … 35 35 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, 36 36 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, 37 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" }, 37 38 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, 38 39 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, -
trunk/util/inteltool/inteltool.h
r4905 r5142 2 2 * inteltool - dump all registers on an Intel CPU + chipset based system. 3 3 * 4 * Copyright (C) 2008 by coresystems GmbH4 * Copyright (C) 2008-2010 by coresystems GmbH 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify … … 48 48 #define PCI_DEVICE_ID_INTEL_82810 0x7120 49 49 #define PCI_DEVICE_ID_INTEL_82810DC 0x7122 50 #define PCI_DEVICE_ID_INTEL_82830M 0x3575 50 51 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 51 52 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 -
trunk/util/inteltool/memory.c
r4905 r5142 2 2 * inteltool - dump all registers on an Intel CPU + chipset based system. 3 3 * 4 * Copyright (C) 2008 by coresystems GmbH4 * Copyright (C) 2008-2010 by coresystems GmbH 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify … … 51 51 case PCI_DEVICE_ID_INTEL_82810: 52 52 case PCI_DEVICE_ID_INTEL_82810DC: 53 case PCI_DEVICE_ID_INTEL_82830M: 53 54 printf("This northbrigde does not have MCHBAR.\n"); 54 55 return 1; -
trunk/util/inteltool/pcie.c
r4905 r5142 2 2 * inteltool - dump all registers on an Intel CPU + chipset based system. 3 3 * 4 * Copyright (C) 2008 by coresystems GmbH4 * Copyright (C) 2008-2010 by coresystems GmbH 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify … … 48 48 case PCI_DEVICE_ID_INTEL_82810: 49 49 case PCI_DEVICE_ID_INTEL_82810DC: 50 case PCI_DEVICE_ID_INTEL_82830M: 50 51 printf("This northbrigde does not have EPBAR.\n"); 51 52 return 1; … … 98 99 case PCI_DEVICE_ID_INTEL_82810: 99 100 case PCI_DEVICE_ID_INTEL_82810DC: 101 case PCI_DEVICE_ID_INTEL_82830M: 100 102 printf("This northbrigde does not have DMIBAR.\n"); 101 103 return 1; -
trunk/util/inteltool/powermgt.c
r4694 r5142 2 2 * inteltool - dump all registers on an Intel CPU + chipset based system. 3 3 * 4 * Copyright (C) 2008 by coresystems GmbH4 * Copyright (C) 2008-2010 by coresystems GmbH 5 5 * written by Stefan Reinauer <stepan@coresystems.de> 6 6 * … … 146 146 }; 147 147 148 static const io_register_t ich4_pm_registers[] = { 149 { 0x00, 2, "PM1_STS" }, 150 { 0x02, 2, "PM1_EN" }, 151 { 0x04, 4, "PM1_CNT" }, 152 { 0x08, 4, "PM1_TMR" }, 153 { 0x0c, 4, "RESERVED" }, 154 { 0x10, 4, "PROC_CNT" }, 155 #if DANGEROUS_REGISTERS 156 /* These registers return 0 on read, but reading them may cause 157 * the system to enter C2/C3/C4 state, which might hang the system. 158 */ 159 { 0x14, 1, "LV2 (Mobile)" }, 160 { 0x15, 1, "LV3 (Mobile)" }, 161 { 0x16, 1, "LV4 (Mobile)" }, 162 #endif 163 { 0x17, 1, "RESERVED" }, 164 { 0x18, 4, "RESERVED" }, 165 { 0x1c, 4, "RESERVED" }, 166 { 0x20, 1, "PM2_CNT (Mobile)" }, 167 { 0x21, 1, "RESERVED" }, 168 { 0x22, 2, "RESERVED" }, 169 { 0x24, 4, "RESERVED" }, 170 { 0x28, 4, "GPE0_STS" }, 171 { 0x2C, 4, "GPE0_EN" }, 172 { 0x30, 4, "SMI_EN" }, 173 { 0x34, 4, "SMI_STS" }, 174 { 0x38, 2, "ALT_GP_SMI_EN" }, 175 { 0x3a, 2, "ALT_GP_SMI_STS" }, 176 { 0x3c, 4, "RESERVED" }, 177 { 0x40, 2, "MON_SMI" }, 178 { 0x42, 2, "RESERVED" }, 179 { 0x44, 2, "DEVACT_STS" }, 180 { 0x46, 2, "RESERVED" }, 181 { 0x48, 4, "DEVTRAP_EN" }, 182 { 0x4c, 2, "BUS_ADDR_TRACK" }, 183 { 0x4e, 2, "BUS_CYC_TRACK" }, 184 { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" }, 185 { 0x51, 1, "RESERVED" }, 186 { 0x52, 2, "RESERVED" }, 187 { 0x54, 4, "RESERVED" }, 188 { 0x58, 4, "RESERVED" }, 189 { 0x5c, 4, "RESERVED" }, 190 /* Here start the TCO registers */ 191 { 0x60, 1, "TCO_RLD" }, 192 { 0x61, 1, "TCO_TMR" }, 193 { 0x62, 1, "TCO_DAT_IN" }, 194 { 0x63, 1, "TCO_DAT_OUT" }, 195 { 0x64, 2, "TCO1_STS" }, 196 { 0x66, 2, "TCO2_STS" }, 197 { 0x68, 2, "TCO1_CNT" }, 198 { 0x6a, 2, "TCO2_CNT" }, 199 { 0x6c, 2, "TCO_MESSAGE" }, 200 { 0x6e, 1, "TCO_WDSTATUS" }, 201 { 0x6f, 1, "RESERVED" }, 202 { 0x70, 1, "SW_IRQ_GEN" }, 203 { 0x71, 1, "RESERVED" }, 204 { 0x72, 2, "RESERVED" }, 205 { 0x74, 4, "RESERVED" }, 206 { 0x78, 4, "RESERVED" }, 207 { 0x7c, 4, "RESERVED" }, 208 }; 209 148 210 static const io_register_t ich0_pm_registers[] = { 149 211 { 0x00, 2, "PM1_STS" }, … … 270 332 size = ARRAY_SIZE(ich8_pm_registers); 271 333 break; 334 case PCI_DEVICE_ID_INTEL_ICH4: 335 pmbase = pci_read_word(sb, 0x40) & 0xfffc; 336 pm_registers = ich4_pm_registers; 337 size = ARRAY_SIZE(ich4_pm_registers); 338 break; 272 339 case PCI_DEVICE_ID_INTEL_ICH0: 273 340 pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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