Changeset 5136


Ignore:
Timestamp:
Feb 22, 2010, 7:09:43 AM (5 years ago)
Author:
stepan
Message:

This is a general cleanup patch

  • drop include/part and move files to include/
  • get rid lots of warnings
  • make resource allocator happy with w83627thg
  • trivial cbmem resume fix
  • fix payload and log level settings in abuild
  • fix kontron mptable for virtual wire mode
  • drop some dead includes and dead code.

Signed-off-by: Stefan Reinauer <stepan@…>
Acked-by: Ronald G. Minnich <rminnich@…>

Location:
trunk
Files:
4 added
5 deleted
70 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/arch/i386/boot/acpi.c

    r5127 r5136  
    488488u8 acpi_slp_type = 0;
    489489
    490 int acpi_is_wakeup(void)
     490static int acpi_is_wakeup(void)
    491491{
    492492        return (acpi_slp_type == 3);
     
    601601
    602602        /* copy wakeup trampoline in place */
    603         memcpy(WAKEUP_BASE, &__wakeup, &__wakeup_size);
     603        memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
    604604
    605605        acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
  • trunk/src/arch/i386/boot/coreboot_table.c

    r5135 r5136  
    2525#include <boot/tables.h>
    2626#include <boot/coreboot_tables.h>
    27 #include "coreboot_table.h"
     27#include <arch/coreboot_tables.h>
    2828#include <string.h>
    2929#include <version.h>
  • trunk/src/arch/i386/boot/pirq_routing.c

    r4778 r5136  
    44#include <device/pci.h>
    55
    6 #if (CONFIG_DEBUG==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
     6#ifndef CONFIG_IRQ_SLOT_COUNT
     7#warning "CONFIG_IRQ_SLOT_COUNT is not defined. PIRQ won't work correctly."
     8#endif
     9
     10#if CONFIG_DEBUG
    711static void check_pirq_routing_table(struct irq_routing_table *rt)
    812{
     
    1317        printk_info("Checking Interrupt Routing Table consistency...\n");
    1418
    15 #if defined(CONFIG_IRQ_SLOT_COUNT)
    1619        if (sizeof(struct irq_routing_table) != rt->size) {
    1720                printk_warning("Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n",
     
    2124                rt->size=sizeof(struct irq_routing_table);
    2225        }
    23 #endif
    2426
    2527        for (i = 0; i < rt->size; i++)
     
    8082        return 0;
    8183}
    82 #else
    83 #define verify_copy_pirq_routing_table(addr)
    8484#endif
    8585
    86 #if CONFIG_GENERATE_PIRQ_TABLE==1
    8786unsigned long copy_pirq_routing_table(unsigned long addr)
    8887{
     
    9998        return addr + intel_irq_routing_table.size;
    10099}
    101 #endif
    102100
    103 #if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
     101#if CONFIG_PIRQ_ROUTE
    104102void pirq_routing_irqs(unsigned long addr)
    105103{
  • trunk/src/arch/i386/boot/tables.c

    r4878 r5136  
    2424#include <boot/tables.h>
    2525#include <boot/coreboot_tables.h>
     26#include <arch/coreboot_tables.h>
    2627#include <arch/pirq_routing.h>
    2728#include <arch/smp/mpspec.h>
     
    2930#include <string.h>
    3031#include <cpu/x86/multiboot.h>
    31 #include "coreboot_table.h"
    3232#include <cbmem.h>
    3333#include <lib.h>
     
    168168                        acpi_write_rsdp(low_rsdp,
    169169                                (acpi_rsdt_t *)(high_rsdp->rsdt_address),
    170                                 (acpi_xsdt_t *)(high_rsdp->xsdt_address));
     170                                (acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address));
    171171                } else {
    172172                        printk_err("ERROR: Didn't find RSDP in high table.\n");
  • trunk/src/arch/i386/include/arch/acpi.h

    r5130 r5136  
    356356
    357357
    358 /* These are implemented by the target port */
     358/* These are implemented by the target port or north/southbridge*/
    359359unsigned long write_acpi_tables(unsigned long addr);
    360360unsigned long acpi_fill_madt(unsigned long current);
     
    415415#endif
    416416
     417/* northbridge/amd/amdfam10/amdfam10_acpi.c */
    417418unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current);
     419/* cpu/intel/speedstep/acpi.c */
     420void generate_cpu_entries(void);
    418421
    419422#define ACPI_WRITE_MADT_IOAPIC(dev,id)                  \
  • trunk/src/arch/i386/include/arch/smp/mpspec.h

    r4686 r5136  
    3232        unsigned char mpf_feature1;     /* Standard or configuration ?  */
    3333        unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
     34#define MP_FEATURE_VIRTUALWIRE (1 << 7)
     35#define MP_FEATURE_PIC         (0 << 7)
    3436        unsigned char mpf_feature3;     /* Unused (0)                   */
    3537        unsigned char mpf_feature4;     /* Unused (0)                   */
  • trunk/src/arch/i386/lib/console_printk.c

    r4794 r5136  
    1 
    2 extern int do_printk(int msg_level, const char *fmt, ...);
    31
    42#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
  • trunk/src/arch/i386/lib/cpu.c

    r4300 r5136  
    225225        info = cpu_info();
    226226
    227         printk_notice("Initializing CPU #%ld\n", info->index);
     227        printk_info("Initializing CPU #%ld\n", info->index);
    228228
    229229        cpu = info->cpu;
  • trunk/src/boot/hardwaremain.c

    r5102 r5136  
    3232#include <delay.h>
    3333#include <stdlib.h>
    34 #include <part/hard_reset.h>
    35 #include <part/init_timer.h>
     34#include <reset.h>
    3635#include <boot/tables.h>
    3736#include <boot/elf.h>
  • trunk/src/boot/selfboot.c

    r4912 r5136  
    2020
    2121#include <console/console.h>
    22 #include <part/fallback_boot.h>
     22#include <fallback.h>
    2323#include <boot/elf.h>
    2424#include <boot/elf_boot.h>
  • trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c

    r4997 r5136  
    5555
    5656        /* No servicable parts below this line .. */
    57 
    58 #if CAR_DEBUG
     57#ifdef CAR_DEBUG
    5958        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
    6059        unsigned v_esp;
  • trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c

    r4997 r5136  
    5656        /* No servicable parts below this line .. */
    5757
    58 #if CAR_DEBUG
     58#ifdef CAR_DEBUG
    5959        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
    6060        unsigned v_esp;
  • trunk/src/cpu/x86/car/copy_and_run.c

    r5111 r5136  
    1 /* Copyright (C) 2009 coresystems GmbH
    2    (Written by Patrick Georgi <patrick.georgi@coresystems.de> for coresystems GmbH
    3 */
     1/*
     2 * This file is part of the coreboot project.
     3 *
     4 * Copyright (C) 2009-2010 coresystems GmbH
     5 * Written by Patrick Georgi <patrick.georgi@coresystems.de>
     6 * for coresystems GmbH
     7 *
     8 * This program is free software; you can redistribute it and/or
     9 * modify it under the terms of the GNU General Public License as
     10 * published by the Free Software Foundation; version 2 of
     11 * the License.
     12 *
     13 * This program is distributed in the hope that it will be useful,
     14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16 * GNU General Public License for more details.
     17 *
     18 * You should have received a copy of the GNU General Public License
     19 * along with this program; if not, write to the Free Software
     20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
     21 * MA 02110-1301 USA
     22 */
    423
    5 void cbfs_and_run_core(char*, unsigned ebp);
     24void cbfs_and_run_core(const char *, unsigned ebp);
    625
    726static void copy_and_run(unsigned cpu_reset)
  • trunk/src/devices/hypertransport.c

    r4890 r5136  
    3535#include <device/pci_ids.h>
    3636#include <device/hypertransport.h>
    37 #include <part/hard_reset.h>
    38 #include <part/fallback_boot.h>
    3937
    4038/* The hypertransport link is already optimized in pre-ram code
  • trunk/src/devices/pci_device.c

    r4995 r5136  
    3333#include <device/pci.h>
    3434#include <device/pci_ids.h>
    35 #include <part/hard_reset.h>
    36 #include <part/fallback_boot.h>
    3735#include <delay.h>
    3836#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
  • trunk/src/devices/pnp_device.c

    r3964 r5136  
    241241                resource->size = 1;
    242242                resource->flags |= IORESOURCE_DRQ;
    243         }       
     243        }
     244        /* These are not IRQs, but set the flag to have the
     245         * resource allocator do the right thing
     246         */
     247        if (info->flags & PNP_EN) {
     248                resource = new_resource(dev, PNP_IDX_EN);
     249                resource->size = 1;
     250                resource->flags |= IORESOURCE_IRQ;
     251        }
     252        if (info->flags & PNP_MSC0) {
     253                resource = new_resource(dev, PNP_IDX_MSC0);
     254                resource->size = 1;
     255                resource->flags |= IORESOURCE_IRQ;
     256        }
     257        if (info->flags & PNP_MSC1) {
     258                resource = new_resource(dev, PNP_IDX_MSC1);
     259                resource->size = 1;
     260                resource->flags |= IORESOURCE_IRQ;
     261        }
    244262}
    245263
  • trunk/src/devices/root_device.c

    r4756 r5136  
    2626#include <device/device.h>
    2727#include <device/pci.h>
    28 #include <part/hard_reset.h>
     28#include <reset.h>
    2929
    3030/**
  • trunk/src/drivers/generic/debug/debug_dev.c

    r4781 r5136  
    66#include <device/pci_ops.h>
    77#include <cpu/x86/msr.h>
    8 #include <part/hard_reset.h>
     8#include <reset.h>
    99#include <delay.h>
    1010#include "chip.h"
  • trunk/src/drivers/i2c/adm1026/adm1026.c

    r4588 r5136  
    55#include <device/pci_ids.h>
    66#include <device/pci_ops.h>
    7 #include <part/hard_reset.h>
    87#include <cpu/x86/msr.h>
    98#include "chip.h"
  • trunk/src/drivers/i2c/adm1027/adm1027.c

    r2663 r5136  
    55#include <device/pci_ids.h>
    66#include <device/pci_ops.h>
    7 #include <part/hard_reset.h>
    87#include <cpu/x86/msr.h>
    98#include "chip.h"
  • trunk/src/include/cpu/cpu.h

    r4890 r5136  
    1818#if CONFIG_HAVE_SMI_HANDLER
    1919void smm_init(void);
     20void smm_lock(void);
     21void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
    2022#endif
    2123
  • trunk/src/include/cpu/x86/bist.h

    r2589 r5136  
    22#define CPU_X86_BIST_H
    33
    4 static void report_bist_failure(unsigned long bist)
     4static void report_bist_failure(u32 bist)
    55{
    66        if (bist != 0) {
  • trunk/src/include/cpu/x86/lapic.h

    r4921 r5136  
    6161static inline __attribute__((always_inline)) void stop_this_cpu(void)
    6262{
    63 
    6463        /* Called by an AP when it is ready to halt and wait for a new task */
    6564        for(;;) {
     
    6766        }
    6867}
     68#else
     69void stop_this_cpu(void);
    6970#endif
    7071
  • trunk/src/include/cpu/x86/tsc.h

    r4921 r5136  
    2525        return val;
    2626}
    27 
    28 void init_timer(void);
    2927#endif
    3028
    31 
    3229#endif /* CPU_X86_TSC_H */
  • trunk/src/include/delay.h

    r4890 r5136  
    11#ifndef DELAY_H
    22#define DELAY_H
     3
    34#if !defined( __ROMCC__)
     5
     6#if CONFIG_HAVE_INIT_TIMER == 1
     7void init_timer(void);
     8#else
     9#define init_timer() do{} while(0)
     10#endif
    411
    512void udelay(unsigned usecs);
  • trunk/src/include/device/pnp.h

    r4000 r5136  
    3434        unsigned function;
    3535        unsigned flags;
    36 #define PNP_IO0  0x01
    37 #define PNP_IO1  0x02
    38 #define PNP_IO2  0x04
    39 #define PNP_IO3  0x08
    40 #define PNP_IRQ0 0x10
    41 #define PNP_IRQ1 0x20
    42 #define PNP_DRQ0 0x40
    43 #define PNP_DRQ1 0x80
     36#define PNP_IO0  0x001
     37#define PNP_IO1  0x002
     38#define PNP_IO2  0x004
     39#define PNP_IO3  0x008
     40#define PNP_IRQ0 0x010
     41#define PNP_IRQ1 0x020
     42#define PNP_DRQ0 0x040
     43#define PNP_DRQ1 0x080
     44#define PNP_EN   0x100
     45#define PNP_MSC0 0x200
     46#define PNP_MSC1 0x400
    4447        struct io_info io0, io1, io2, io3;
    4548};
  • trunk/src/include/device/pnp_def.h

    r1662 r5136  
    22#define DEVICE_PNP_DEF_H
    33
     4#define PNP_IDX_EN   0x30
    45#define PNP_IDX_IO0  0x60
    56#define PNP_IDX_IO1  0x62
     
    1011#define PNP_IDX_DRQ0 0x74
    1112#define PNP_IDX_DRQ1 0x75
    12 
     13#define PNP_IDX_MSC0 0xf0
     14#define PNP_IDX_MSC1 0xf1
    1315
    1416#endif /* DEVICE_PNP_DEF_H */
  • trunk/src/lib/cbmem.c

    r4939 r5136  
    185185                if (!cbmem_reinit(high_tables_base)) {
    186186                        /* Something went wrong, our high memory area got wiped */
    187                         acpi_slp_type == 0;
     187                        acpi_slp_type = 0;
    188188                        cbmem_init(high_tables_base, high_tables_size);
    189189                }
  • trunk/src/lib/fallback_boot.c

    r5135 r5136  
    11#include <console/console.h>
    2 #include <part/fallback_boot.h>
    3 #include <part/watchdog.h>
     2#include <fallback.h>
     3#include <watchdog.h>
    44#include <pc80/mc146818rtc.h>
    55#include <arch/io.h>
  • trunk/src/lib/ramtest.c

    r4661 r5136  
    3131         */
    3232#if CONFIG_USE_PRINTK_IN_CAR
    33         printk_debug("DRAM fill: 0x%08x-0x%08x\r\n", start, stop);
     33        printk_debug("DRAM fill: 0x%08lx-0x%08lx\r\n", start, stop);
    3434#else
    3535        print_debug("DRAM fill: ");
     
    4343                if (!(addr & 0xfffff)) {
    4444#if CONFIG_USE_PRINTK_IN_CAR
    45                         printk_debug("%08x \r", addr);
     45                        printk_debug("%08lx \r", addr);
    4646#else
    4747                        print_debug_hex32(addr);
     
    5353        /* Display final address */
    5454#if CONFIG_USE_PRINTK_IN_CAR
    55         printk_debug("%08x\r\nDRAM filled\r\n", addr);
     55        printk_debug("%08lx\r\nDRAM filled\r\n", addr);
    5656#else
    5757        print_debug_hex32(addr);
     
    6868         */
    6969#if CONFIG_USE_PRINTK_IN_CAR
    70         printk_debug("DRAM verify: 0x%08x-0x%08x\r\n", start, stop);
     70        printk_debug("DRAM verify: 0x%08lx-0x%08lx\r\n", start, stop);
    7171#else
    7272        print_debug("DRAM verify: ");
     
    8181                if (!(addr & 0xfffff)) {
    8282#if CONFIG_USE_PRINTK_IN_CAR
    83                         printk_debug("%08x \r", addr);
     83                        printk_debug("%08lx \r", addr);
    8484#else
    8585                        print_debug_hex32(addr);
     
    9191                        /* Display address with error */
    9292#if CONFIG_USE_PRINTK_IN_CAR
    93                         printk_err("Fail: @0x%08x Read value=0x%08x\r\n", addr, value);
     93                        printk_err("Fail: @0x%08lx Read value=0x%08lx\r\n", addr, value);
    9494#else
    9595                        print_err("Fail: @0x");
     
    112112        /* Display final address */
    113113#if CONFIG_USE_PRINTK_IN_CAR
    114         printk_debug("%08x", addr);
     114        printk_debug("%08lx", addr);
    115115#else
    116116        print_debug_hex32(addr);
     
    143143         */
    144144#if CONFIG_USE_PRINTK_IN_CAR
    145         printk_debug("Testing DRAM : %08x - %08x\r\n", start, stop);
     145        printk_debug("Testing DRAM : %08lx - %08lx\r\n", start, stop);
    146146#else
    147147        print_debug("Testing DRAM : ");
  • trunk/src/mainboard/intel/d945gclf/Kconfig

    r5052 r5136  
    9292        default 2
    9393        depends on BOARD_INTEL_D945GCLF
     94
     95config HAVE_ACPI_SLIC
     96        bool
     97        default n
     98        depends on BOARD_INTEL_D945GCLF
     99
  • trunk/src/mainboard/intel/d945gclf/acpi_tables.c

    r5018 r5136  
    3636unsigned long acpi_create_slic(unsigned long current);
    3737#endif
    38 void generate_cpu_entries(void); // from cpu/intel/speedstep
    39 unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
    4038
    4139#if OLD_ACPI
  • trunk/src/mainboard/kontron/986lcd-m/Kconfig

    r5051 r5136  
    7777        default "amipci_01.20"
    7878        depends on BOARD_KONTRON_986LCD_M
     79
     80config HAVE_ACPI_SLIC
     81        bool
     82        default n
     83        depends on BOARD_KONTRON_986LCD_M
     84
  • trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c

    r4861 r5136  
    3333
    3434extern unsigned char AmlCode[];
    35 #if HAVE_ACPI_SLIC
     35#if CONFIG_HAVE_ACPI_SLIC
    3636unsigned long acpi_create_slic(unsigned long current);
    3737#endif
    38 void generate_cpu_entries(void); // from cpu/intel/speedstep
    3938
    4039#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
     
    143142        acpi_fadt_t *fadt;
    144143        acpi_facs_t *facs;
    145 #if HAVE_ACPI_SLIC
     144#if CONFIG_HAVE_ACPI_SLIC
    146145        acpi_header_t *slic;
    147146#endif
     
    217216        for (i=0; i < dsdt->length; i++) {
    218217                if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
    219                         printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
     218                        printk_debug("ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
    220219                        *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
    221220                        break;
     
    224223
    225224        /* And fill it */
    226         acpi_create_gnvs(current);
     225        acpi_create_gnvs((global_nvs_t *)current);
    227226
    228227        current += 0x100;
     
    239238                     dsdt->length);
    240239
    241 #if HAVE_ACPI_SLIC
     240#if CONFIG_HAVE_ACPI_SLIC
    242241        printk_debug("ACPI:     * SLIC\n");
    243242        slic = (acpi_header_t *)current;
  • trunk/src/mainboard/kontron/986lcd-m/devicetree.cb

    r4925 r5136  
    103103                                                 io 0x60 = 0x2e8
    104104                                                irq 0x70 = 10
     105                                                irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
    105106                                        end
    106107                                        device pnp 4e.5 off             # Keyboard
  • trunk/src/mainboard/kontron/986lcd-m/mainboard.c

    r5042 r5136  
    2727#include <pc80/mc146818rtc.h>
    2828#include <arch/io.h>
     29#include <arch/coreboot_tables.h>
    2930#include "chip.h"
    30 
    31 int add_northbridge_resources(struct lb_memory *mem);
    3231
    3332int add_mainboard_resources(struct lb_memory *mem)
  • trunk/src/mainboard/kontron/986lcd-m/mptable.c

    r5043 r5136  
    2828#include <stdint.h>
    2929
    30 void *smp_write_config_table(void *v)
     30static void *smp_write_config_table(void *v)
    3131{
    3232        static const char sig[4] = "PCMP";
     
    3737        int i;
    3838        int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
     39        int ioapic_id;
    3940
    4041        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
     
    8788
    8889        /* I/O APICs:   APIC ID Version State           Address */
    89         smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
     90        ioapic_id = 2;
     91        smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000);
    9092
    9193        /* Legacy Interrupts */
    9294
    9395        /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
    94         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x0);
    95         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, 0x2, 0x1);
    96         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, 0x2, 0x2);
    97         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, 0x2, 0x3);
    98         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, 0x2, 0x4);
    99         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, 0x2, 0x8);
    100         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, 0x2, 0x9);
    101         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, 0x2, 0xa);
    102         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, 0x2, 0xb);
    103         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, 0x2, 0xc);
    104         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, 0x2, 0xd);
    105         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, 0x2, 0xe);
    106         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, 0x2, 0xf);
     96        smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
     97        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
     98        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
     99        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
     100        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
     101        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,       isa_bus, 0x8, ioapic_id, 0x8);
     102        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
     103        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
     104        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
     105        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
     106        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
     107        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
     108        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
    107109
    108110        /* Builtin devices on Bus 0 */
    109         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
    110         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
    111         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
    112         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
    113         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
    114         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
    115         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
    116         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
    117         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
     111        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
     112        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
     113        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
     114        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
     115        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
     116        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
     117        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
     118        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
     119        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
     120        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
    118121
    119         /* Firewire 4:0.0 */
     122        /* Internal PCI bus (Firewire, PCI slot) */
    120123        if (firewire) {
    121                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, 0x2, 0x10);
     124                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
     125                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
    122126        }
    123127
     
    125129                /* Old riser card */
    126130                // riser slot top 5:8.0
    127                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, 0x2, 0x14);
     131                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
    128132                // riser slot middle 5:9.0
    129                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, 0x2, 0x15);
     133                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
    130134                // riser slot bottom 5:a.0
    131                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, 0x2, 0x16);
     135                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
    132136
    133137                /* New Riser Card */
    134                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, 0x2, 0x14);
    135                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, 0x2, 0x15);
    136                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, 0x2, 0x16);
     138                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
     139                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
     140                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
    137141        }
    138142
     143        /* PCIe slot */
     144        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
     145        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
     146
    139147        /* Onboard Ethernet */
    140         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
     148        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
    141149
    142150        /* Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
     
    153161}
    154162
     163/* MP table generation in coreboot is not very well designed;
     164 * One of the issues is that it knows nothing about Virtual
     165 * Wire mode, which everyone uses since a decade or so. This
     166 * function fixes up our floating table. This spares us doing
     167 * a half-baked fix of adding a new parameter to 200+ calls
     168 * to smp_write_floating_table()
     169 */
     170static void fixup_virtual_wire(void *v)
     171{
     172        struct intel_mp_floating *mf = v;
     173
     174        mf->mpf_checksum = 0;
     175        mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE;
     176        mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16);
     177}
     178
    155179unsigned long write_smp_table(unsigned long addr)
    156180{
    157181        void *v;
    158182        v = smp_write_floating_table(addr);
     183        fixup_virtual_wire(v);
    159184        return (unsigned long)smp_write_config_table(v);
    160185}
  • trunk/src/mainboard/kontron/986lcd-m/romstage.c

    r5092 r5136  
    22 * This file is part of the coreboot project.
    33 *
    4  * Copyright (C) 2007-2009 coresystems GmbH
     4 * Copyright (C) 2007-2010 coresystems GmbH
    55 *
    66 * This program is free software; you can redistribute it and/or
     
    4949#include "pc80/mc146818rtc_early.c"
    5050
     51#include <console/console.h>
    5152#include "pc80/serial.c"
    5253#include "arch/i386/lib/console.c"
     
    368369#include "lib/cbmem.c"
    369370
     371#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
     372
    370373void real_main(unsigned long bist)
    371374{
     
    478481                 */
    479482                if (resume_backup_memory)
    480                         memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
     483                        memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
    481484
    482485                /* Magic for S3 resume */
     
    486489}
    487490
    488 #include "cpu/intel/model_6ex/cache_as_ram_disable.c"
  • trunk/src/mainboard/roda/rk886ex/Kconfig

    r5052 r5136  
    7474        default 0x6886
    7575        depends on BOARD_RODA_RK886EX
     76
     77config HAVE_ACPI_SLIC
     78        bool
     79        default n
     80        depends on BOARD_RODA_RK886EX
     81
  • trunk/src/mainboard/roda/rk886ex/acpi_tables.c

    r5031 r5136  
    3535unsigned long acpi_create_slic(unsigned long current);
    3636#endif
    37 void generate_cpu_entries(void); // from cpu/intel/speedstep
    38 unsigned long acpi_fill_mcfg(unsigned long current); // from northbridge/intel/i945
    3937
    4038#define OLD_ACPI 0
  • trunk/src/mainboard/via/epia-m700/acpi_tables.c

    r4778 r5136  
    4040
    4141extern u32 wake_vec;
    42 extern u8 acpi_sleep_type;
    4342
    4443/*
     
    204203}
    205204
    206 int acpi_is_wakeup(void)
    207 {
    208         return (acpi_sleep_type == 3);
    209 }
  • trunk/src/mainboard/via/epia-m700/wakeup.c

    r4397 r5136  
    3232#include <console/console.h>
    3333#include <delay.h>
    34 #include <part/init_timer.h>    /* for jason_tsc_count_end */
    3534#include "wakeup.h"
    3635
  • trunk/src/northbridge/amd/amdfam10/misc_control.c

    r4381 r5136  
    3131#include <device/pci_ids.h>
    3232#include <device/pci_ops.h>
    33 #include <part/hard_reset.h>
    3433#include <pc80/mc146818rtc.h>
    3534#include <bitops.h>
  • trunk/src/northbridge/amd/amdk8/misc_control.c

    r4394 r5136  
    1515#include <device/pci_ids.h>
    1616#include <device/pci_ops.h>
    17 #include <part/hard_reset.h>
     17#include <reset.h>
    1818#include <pc80/mc146818rtc.h>
    1919#include <bitops.h>
  • trunk/src/northbridge/intel/e7520/pciexp_porta.c

    r2891 r5136  
    77#include <arch/io.h>
    88#include "chip.h"
    9 #include <part/hard_reset.h>
     9#include <reset.h>
    1010                                                           
    1111typedef struct northbridge_intel_e7520_config config_t;
  • trunk/src/northbridge/intel/i3100/pciexp_porta.c

    r3536 r5136  
    2929#include <arch/io.h>
    3030#include "chip.h"
    31 #include <part/hard_reset.h>
     31#include <reset.h>
    3232
    3333typedef struct northbridge_intel_i3100_config config_t;
  • trunk/src/northbridge/intel/i3100/pciexp_porta_ep80579.c

    r4615 r5136  
    2929#include <arch/io.h>
    3030#include "chip.h"
    31 #include <part/hard_reset.h>
     31#include <reset.h>
    3232
    3333typedef struct northbridge_intel_i3100_config config_t;
  • trunk/src/northbridge/intel/i945/northbridge.c

    r4861 r5136  
    3232#include "chip.h"
    3333#include "i945.h"
    34 
    35 int get_pcie_bar(u32 *base, u32 *len)
     34#include <arch/coreboot_tables.h>
     35
     36static int get_pcie_bar(u32 *base, u32 *len)
    3637{
    3738        device_t dev;
  • trunk/src/northbridge/intel/i945/raminit.c

    r5092 r5136  
    399399        }
    400400
    401         /* The chipset might be able to do this. What the heck, legacy bios
    402          * just beeps when a single DIMM is in the Channel 1 socket. So let's
    403          * not bother until someone needs this enough to cope with it.
    404          */
    405401        if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
    406                 printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\n");
     402                printk_info("Channel 0 has no memory populated.\n");
    407403        }
    408404}
     
    455451        int i, j, idx;
    456452        int lowest_common_cas = 0;
    457         int max_ram_speed;
     453        int max_ram_speed = 0;
    458454
    459455        const u8 ddr2_speeds_table[] = {
     
    15941590                        continue;
    15951591
    1596                 printk_spew("DIMM%d has 8 banks.\n");
     1592                printk_spew("DIMM%d has 8 banks.\n", i);
    15971593
    15981594                if (i & 1)
     
    25732569        pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
    25742570
    2575 #if C2_SELF_REFRESH_DISABLE
     2571#ifdef C2_SELF_REFRESH_DISABLE
    25762572
    25772573        if (integrated_graphics) {
  • trunk/src/northbridge/intel/i945/raminit.h

    r4455 r5136  
    6868} __attribute__ ((packed));
    6969
     70void receive_enable_adjust(struct sys_info *sysinfo);
     71
    7072#endif                          /* RAMINIT_H */
  • trunk/src/pc80/mc146818rtc_early.c

    r4381 r5136  
    11#include <pc80/mc146818rtc.h>
    2 #include <part/fallback_boot.h>
     2#include <fallback.h>
    33
    44#ifndef CONFIG_MAX_REBOOT_CNT
  • trunk/src/pc80/serial.c

    r4534 r5136  
    1 #include <part/fallback_boot.h>
    2 
    31/* Base Address */
    42#ifndef CONFIG_TTYS0_BASE
  • trunk/src/pc80/usbdebug_direct_serial.c

    r4788 r5136  
    1616 */
    1717
    18 #include <part/fallback_boot.h>
    1918#include "../lib/usbdebug_direct.c"
    2019
  • trunk/src/southbridge/intel/i3100/i3100_pciexp_portb.c

    r4392 r5136  
    2929#include <arch/io.h>
    3030#include "chip.h"
    31 #include <part/hard_reset.h>
     31#include <reset.h>
    3232
    3333#define PCIE_LCTL 0x50
  • trunk/src/southbridge/intel/i82801gx/Kconfig

    r5039 r5136  
    2121        bool
    2222        select IOAPIC
     23        select USE_WATCHDOG_ON_BOOT
    2324
  • trunk/src/southbridge/intel/i82801gx/i82801gx.h

    r5127 r5136  
    4747extern void i82801gx_enable(device_t dev);
    4848#endif
     49
     50#define MAINBOARD_POWER_OFF     0
     51#define MAINBOARD_POWER_ON      1
     52#define MAINBOARD_POWER_KEEP    2
     53
     54#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
     55#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
     56#endif
     57
     58/* PCI Configuration Space (D30:F0): PCI2PCI */
     59#define PSTS    0x06
     60#define SMLT    0x1b
     61#define SECSTS  0x1e
     62#define INTR    0x3c
     63#define BCTRL   0x3e
     64#define   SBR   (1 << 6)
     65#define   SEE   (1 << 1)
     66#define   PERE  (1 << 0)
    4967
    5068/* PCI Configuration Space (D31:F0): LPC */
  • trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c

    r5092 r5136  
    3434typedef struct southbridge_intel_i82801gx_config config_t;
    3535
    36 static int set_bits(u8 * port, u32 mask, u32 val)
     36static int set_bits(u32 port, u32 mask, u32 val)
    3737{
    3838        u32 reg32;
     
    6363}
    6464
    65 static int codec_detect(u8 * base)
     65static int codec_detect(u32 base)
    6666{
    6767        u32 reg32;
     
    117117 */
    118118
    119 static int wait_for_ready(u8 *base)
     119static int wait_for_ready(u32 base)
    120120{
    121121        /* Use a 50 usec timeout - the Linux kernel uses the
     
    140140 */
    141141
    142 static int wait_for_valid(u8 *base)
     142static int wait_for_valid(u32 base)
    143143{
    144144        u32 reg32;
     
    164164}
    165165
    166 static void codec_init(struct device *dev, u8 * base, int addr)
     166static void codec_init(struct device *dev, u32 base, int addr)
    167167{
    168168        u32 reg32;
     
    208208}
    209209
    210 static void codecs_init(struct device *dev, u8 * base, u32 codec_mask)
     210static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
    211211{
    212212        int i;
     
    219219static void azalia_init(struct device *dev)
    220220{
    221         u8 *base;
     221        u32 base;
    222222        struct resource *res;
    223223        u32 codec_mask;
     
    304304        // NOTE this will break as soon as the Azalia get's a bar above
    305305        // 4G. Is there anything we can do about it?
    306         base = (u8 *) ((u32)res->base);
     306        base = (u32)res->base;
    307307        printk_debug("Azalia: base = %08x\n", (u32)base);
    308308        codec_mask = codec_detect(base);
  • trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c

    r5026 r5136  
    2828#include <arch/io.h>
    2929#include "i82801gx.h"
    30 #include "i82801gx_power.h"
    3130
    3231#define NMI_OFF 0
  • trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c

    r4538 r5136  
    2323#include <device/pci.h>
    2424#include <device/pci_ids.h>
     25#include "i82801gx.h"
    2526
    2627static void pci_init(struct device *dev)
     
    3536
    3637        /* This device has no interrupt */
    37         pci_write_config8(dev, 0x3c, 0xff);
     38        pci_write_config8(dev, INTR, 0xff);
    3839
    3940        /* disable parity error response and SERR */
    40         reg16 = pci_read_config16(dev, 0x3e);
     41        reg16 = pci_read_config16(dev, BCTRL);
    4142        reg16 &= ~(1 << 0);
    4243        reg16 &= ~(1 << 1);
    43         pci_write_config16(dev, 0x3e, reg16);
     44        pci_write_config16(dev, BCTRL, reg16);
    4445
    4546        /* Master Latency Count must be set to 0x04! */
    46         reg8 = pci_read_config8(dev, 0x1b);
     47        reg8 = pci_read_config8(dev, SMLT);
    4748        reg8 &= 0x07;
    4849        reg8 |= (0x04 << 3);
    49         pci_write_config8(dev, 0x1b, reg8);
     50        pci_write_config8(dev, SMLT, reg8);
    5051
    5152        /* Will this improve throughput of bus masters? */
     
    5354
    5455        /* Clear errors in status registers */
    55         reg16 = pci_read_config16(dev, 0x06);
     56        reg16 = pci_read_config16(dev, PSTS);
    5657        //reg16 |= 0xf900;
    57         pci_write_config16(dev, 0x06, reg16);
     58        pci_write_config16(dev, PSTS, reg16);
    5859
    59         reg16 = pci_read_config16(dev, 0x1e);
     60        reg16 = pci_read_config16(dev, SECSTS);
    6061        // reg16 |= 0xf900;
    61         pci_write_config16(dev, 0x1e, reg16);
     62        pci_write_config16(dev, SECSTS, reg16);
    6263}
    6364
  • trunk/src/southbridge/intel/i82801gx/i82801gx_pcie.c

    r4538 r5136  
    7676        pci_write_config16(dev, 0x50, reg16);
    7777
    78 #if EVEN_MORE_DEBUG
     78#ifdef EVEN_MORE_DEBUG
    7979        reg32 = pci_read_config32(dev, 0x20);
    8080        printk_spew("    MBL    = 0x%08x\n", reg32);
  • trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c

    r5016 r5136  
    2020
    2121#include <arch/io.h>
     22#include <reset.h>
    2223
    2324void soft_reset(void)
  • trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c

    r5026 r5136  
    2525#include <console/console.h>
    2626#include <arch/io.h>
     27#include <cpu/cpu.h>
    2728#include <cpu/x86/cache.h>
    2829#include <cpu/x86/smm.h>
     
    238239extern uint8_t smm_relocation_start, smm_relocation_end;
    239240
    240 void smm_relocate(void)
     241static void smm_relocate(void)
    241242{
    242243        u32 smi_en;
     
    318319}
    319320
    320 void smm_install(void)
     321static void smm_install(void)
    321322{
    322323        /* enable the SMM memory window */
  • trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c

    r5026 r5136  
    2828#include <device/pci_def.h>
    2929#include "i82801gx.h"
    30 #include "i82801gx_power.h"
    3130
    3231#define DEBUG_SMI
  • trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c

    r5022 r5136  
    5454        res = find_resource(dev, 0x10);
    5555        base = res->base;
    56         reg32 = read32((u8 *)base + 0x24) | (1 << 2);
    57         write32((u8 *)base + 0x24, reg32);
     56        reg32 = read32(base + 0x24) | (1 << 2);
     57        write32(base + 0x24, reg32);
    5858
    5959        /* workaround */
  • trunk/src/southbridge/intel/i82801gx/i82801gx_watchdog.c

    r3991 r5136  
    2323#include <device/device.h>
    2424#include <device/pci.h>
     25#include <watchdog.h>
    2526
    2627void watchdog_off(void)
  • trunk/src/southbridge/nvidia/ck804/ck804_reset.c

    r4890 r5136  
    55
    66#include <arch/io.h>
    7 #include <part/hard_reset.h>
     7#include <reset.h>
    88
    99#define PCI_DEV(BUS, DEV, FN) ( \
  • trunk/src/southbridge/sis/sis966/sis761.c

    r3964 r5136  
    3535#include <device/pci_ids.h>
    3636#include <device/pci_ops.h>
    37 #include <part/hard_reset.h>
    3837#include <pc80/mc146818rtc.h>
    3938#include <bitops.h>
    4039#include <cpu/amd/model_fxx_rev.h>
    41 
    42 //#include "amdk8.h"
    43 
    4440#include <arch/io.h>
    4541
  • trunk/src/superio/winbond/w83627thg/superio.c

    r4993 r5136  
    103103        { &ops, W83627THG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
    104104        { &ops, W83627THG_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
    105         { &ops, W83627THG_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
     105        { &ops, W83627THG_SP2,  PNP_IO0 | PNP_IRQ0 | PNP_MSC1, { 0x7f8, 0 }, },
    106106        /* No 4 { 0,}, */
    107         { &ops, W83627THG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
     107        { &ops, W83627THG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
    108108        { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
    109109        { &ops, W83627THG_GPIO2,},
    110         { &ops, W83627THG_GPIO3,},
     110        { &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
    111111        { &ops, W83627THG_ACPI, PNP_IRQ0,  },
    112112        { &ops, W83627THG_HWM,  PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
  • trunk/util/abuild/abuild

    r5108 r5136  
    163163                if [ "$PAYLOAD" != "/dev/null" ]; then
    164164                        echo "# CONFIG_PAYLOAD_NONE is not set" >> .config
    165                         echo "CONFIG_PAYLOAD_ELF=\"$PAYLOAD\"" >> .config
     165                        echo "CONFIG_PAYLOAD_ELF=y" >> .config
     166                        echo "CONFIG_FALLBACK_PAYLOAD_FILE=\"$PAYLOAD\"" >> .config
    166167                fi
    167168
    168169                if [ "$loglevel" != "default" ]; then
    169170                        printf "(loglevel override) "
    170                         echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$loglevel=y"
    171                         echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel"
    172                         echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y"
    173                         echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel"
     171                        echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$loglevel=y" >> .config
     172                        echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel" >> .config
     173                        echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y" >> .config
     174                        echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel" >> .config
    174175                fi
    175176        fi
     
    224225        mv .config ${build_dir}/config.build
    225226        mv .xcompile ${build_dir}/xcompile.build
    226         mv ..config.tmp ${build_dir}/config.deps
    227227        cd $TARGET/${VENDOR}_${MAINBOARD}
    228228        etime=`perl -e 'print time();' 2>/dev/null || date +%s`
  • trunk/util/romcc/romcc.c

    r5123 r5136  
    2245022450static int is_imm32(struct triple *imm)
    2245122451{
    22452         return ((imm->op == OP_INTCONST) && (imm->u.cval <= 0xffffffffUL)) ||
     22452        // second condition commented out to prevent compiler warning:
     22453        // imm->u.cval is always 32bit unsigned, so the comparison is
     22454        // always true.
     22455        return ((imm->op == OP_INTCONST) /* && (imm->u.cval <= 0xffffffffUL) */ ) ||
    2245322456                (imm->op == OP_ADDRCONST);
    2245422457       
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