Changeset 5133


Ignore:
Timestamp:
Feb 20, 2010 10:38:16 AM (3 years ago)
Author:
zbao
Message:

trival. All the changes is about comment and spaces.

  1. Delete trailing white spaces.
  2. Change the comment to /* */.
  3. Add some copyright header.
  4. reindent.
  5. delete multi blank lines.

Signed-off-by: Zheng Bao <zheng.bao@…>
Acked-by: Zheng Bao <zheng.bao@…>

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/cpu/x86/lapic/lapic_cpu_init.c

    r4890 r5133  
    2020#if CONFIG_RAMBASE >= 0x100000 
    2121/* This is a lot more paranoid now, since Linux can NOT handle 
    22  * being told there is a CPU when none exists. So any errors  
    23  * will return 0, meaning no CPU.  
     22 * being told there is a CPU when none exists. So any errors 
     23 * will return 0, meaning no CPU. 
    2424 * 
    2525 * We actually handling that case by noting which cpus startup 
    2626 * and not telling anyone about the ones that dont. 
    27  */  
     27 */ 
    2828static unsigned long get_valid_start_eip(unsigned long orig_start_eip) 
    2929{ 
    30         return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000  
     30        return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 
    3131} 
    3232#endif 
    … …  
    4040extern char _secondary_start[]; 
    4141 
    42 static void copy_secondary_start_to_1m_below(void)  
     42static void copy_secondary_start_to_1m_below(void) 
    4343{ 
    4444#if CONFIG_RAMBASE >= 0x100000 
    45         extern char _secondary_start_end[]; 
    46         unsigned long code_size; 
    47         unsigned long start_eip; 
    48  
    49         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S 
    50                 Also We need to copy the _secondary_start to the below 1M region 
    51         */ 
    52         start_eip = get_valid_start_eip((unsigned long)_secondary_start); 
    53         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; 
     45        extern char _secondary_start_end[]; 
     46        unsigned long code_size; 
     47        unsigned long start_eip; 
     48 
     49        /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S 
     50           Also We need to copy the _secondary_start to the below 1M region 
     51        */ 
     52        start_eip = get_valid_start_eip((unsigned long)_secondary_start); 
     53        code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; 
    5454 
    5555#if CONFIG_HAVE_ACPI_RESUME == 1 
    … …  
    5858        lowmem_backup = malloc(code_size); 
    5959        lowmem_backup_ptr = (char *)start_eip; 
    60          
     60 
    6161        if (lowmem_backup == NULL) 
    6262                die("Out of backup memory\n"); 
    6363 
    64         memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); 
    65 #endif 
    66         /* copy the _secondary_start to the ram below 1M*/ 
    67         memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); 
    68  
    69         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); 
     64        memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); 
     65#endif 
     66        /* copy the _secondary_start to the ram below 1M*/ 
     67        memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); 
     68 
     69        printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); 
    7070#endif 
    7171} 
    … …  
    7676        unsigned long send_status, accept_status, start_eip; 
    7777        int j, num_starts, maxlvt; 
    78                  
     78 
    7979        /* 
    8080         * Starting actual IPI sequence... 
    … …  
    9191         * Send IPI 
    9292         */ 
    93          
     93 
    9494        lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT 
    9595                                | LAPIC_DM_INIT); 
    … …  
    105105                printk_err("CPU %ld: First apic write timed out. Disabling\n", 
    106106                         apicid); 
    107                 // too bad.  
     107                // too bad. 
    108108                printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); 
    109109                if (lapic_read(LAPIC_ESR)) { 
    … …  
    123123        /* Send IPI */ 
    124124        lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); 
    125          
     125 
    126126        printk_spew("Waiting for send to finish...\n"); 
    127127        timeout = 0; 
    … …  
    134134                printk_err("CPU %ld: Second apic write timed out. Disabling\n", 
    135135                         apicid); 
    136                 // too bad.  
     136                // too bad. 
    137137                return 0; 
    138138        } 
    … …  
    245245        /* Get an index for the new processor */ 
    246246        index = ++last_cpu_index; 
    247          
     247 
    248248        /* Find end of the new processors stack */ 
    249249#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) 
    250         if(index<1) { // only keep bsp on low  
     250        if(index<1) { // only keep bsp on low 
    251251                stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); 
    252252        } else { 
    … …  
    266266#endif 
    267267 
    268          
     268 
    269269        /* Record the index and which cpu structure we are using */ 
    270270        info = (struct cpu_info *)stack_end; 
    … …  
    340340        printk_spew("Deasserting INIT.\n"); 
    341341        /* Deassert the LAPIC INIT */ 
    342         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));        
     342        lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); 
    343343        lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); 
    344344 
    … …  
    392392        #if CONFIG_SERIAL_CPU_INIT == 0 
    393393                if(cpu==bsp_cpu) { 
    394                         continue;  
     394                        continue; 
    395395                } 
    396396        #endif 
    … …  
    438438                } 
    439439                if (!cpu->initialized) { 
    440                         printk_err("CPU 0x%02x did not initialize!\n",  
     440                        printk_err("CPU 0x%02x did not initialize!\n", 
    441441                                cpu->path.apic.apic_id); 
    442442                } 
    … …  
    481481#endif 
    482482 
    483         cpus_ready_for_init();  
     483        cpus_ready_for_init(); 
    484484 
    485485#if CONFIG_SMP == 1 
    486486        #if CONFIG_SERIAL_CPU_INIT == 0 
    487487        /* start all aps at first, so we can init ECC all together */ 
    488         start_other_cpus(cpu_bus, info->cpu); 
     488        start_other_cpus(cpu_bus, info->cpu); 
    489489        #endif 
    490490#endif 
    491491 
    492         /* Initialize the bootstrap processor */ 
    493         cpu_initialize(); 
     492        /* Initialize the bootstrap processor */ 
     493        cpu_initialize(); 
    494494 
    495495#if CONFIG_SMP == 1 
    496         #if CONFIG_SERIAL_CPU_INIT == 1 
    497         start_other_cpus(cpu_bus, info->cpu); 
    498         #endif 
     496        #if CONFIG_SERIAL_CPU_INIT == 1 
     497        start_other_cpus(cpu_bus, info->cpu); 
     498        #endif 
    499499 
    500500        /* Now wait the rest of the cpus stop*/ 
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