Changeset 5064


Ignore:
Timestamp:
Jan 29, 2010, 8:15:10 PM (6 years ago)
Author:
linux_junkie
Message:

RCA RM4100 and Thomson IP1000 auto.c rework.
Signed-off-by: Joseph Smith <joe@…>
Acked-by: Ronald G. Minnich <rminnich@…>

Location:
trunk/src/mainboard
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/mainboard/rca/rm4100/auto.c

    r4998 r5064  
    22 * This file is part of the coreboot project.
    33 *
    4  * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
     4 * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
    55 *
    66 * This program is free software; you can redistribute it and/or modify
     
    4646
    4747#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
    48 #include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
    4948
    5049/**
    51  * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
     50 * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
    5251 * values have to be set manually, the SO-DIMM socket is located in
    5352 * socket0 (0x50), and the onboard memory is located in socket1 (0x51).
     
    7473
    7574/**
    76  * The AC'97 Audio Controller I/O space registers are read only by default
    77  * so we need to enable them by setting register 0x41 to 0x01.
     75 * Setup mainboard specific registers pre raminit.
    7876 */
    79 static void ac97_io_enable(void)
     77static void mb_early_setup(void)
    8078{
    81         device_t dev;
     79        /* - Hub Interface to PCI Bridge Registers - */
     80        /* 12-Clock Retry Enable */
     81        pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
     82        /* Master Latency Timer Count */
     83        pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
     84        /* I/O Address Base */
     85        pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
    8286
    83         /* Set the ac97 audio device staticly. */
    84         dev = PCI_DEV(0x0, 0x1f, 0x5);
    85 
    86         /* Enable access to the IO space. */
    87         pci_write_config8(dev, 0x41, 0x01);
     87        /* - LPC Interface Bridge Registers - */
     88        /* Delayed Transaction Enable */
     89        pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
     90        /* Disable the TCO Timer system reboot feature */
     91        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
     92        /* CPU Frequency Strap */
     93        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
     94        /* ACPI base address and enable Resource Indicator */
     95        pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
     96        /* Enable the SMBUS */
     97        enable_smbus();
     98        /* ACPI base address and disable Resource Indicator */
     99        pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
     100        /*  ACPI Enable */
     101        pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
    88102}
    89103
     
    103117                }
    104118
     119        /* Set southbridge and superio gpios */
     120        mb_gpio_init();
     121
    105122        smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
    106         mb_gpio_init();
    107123        uart_init();
    108124        console_init();
    109 
    110         enable_smbus();
    111 
    112         /* Prevent the TCO timer from rebooting us */
    113         i82801xx_halt_tco_timer();
    114125
    115126        /* Halt if there was a built in self test failure. */
    116127        report_bist_failure(bist);
    117128
     129        /* Setup mainboard specific registers */
     130        mb_early_setup();
     131
     132        /* SDRAM init */
    118133        sdram_set_registers(memctrl);
    119134        sdram_set_spd_registers(memctrl);
     
    122137        /* Check RAM. */
    123138        /* ram_check(0, 640 * 1024); */
    124         /* ram_check(130048 * 1024, 131072 * 1024); */
    125 
    126         ac97_io_enable();
     139        /* ram_check(64512 * 1024, 65536 * 1024); */
    127140}
  • trunk/src/mainboard/thomson/ip1000/auto.c

    r4998 r5064  
    22 * This file is part of the coreboot project.
    33 *
    4  * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
     4 * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
    55 *
    66 * This program is free software; you can redistribute it and/or modify
     
    4646
    4747#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
    48 #include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
    4948
    5049/**
     
    7473
    7574/**
    76  * The AC'97 Audio Controller I/O space registers are read only by default
    77  * so we need to enable them by setting register 0x41 to 0x01.
     75 * Setup mainboard specific registers pre raminit.
    7876 */
    79 static void ac97_io_enable(void)
     77static void mb_early_setup(void)
    8078{
    81         device_t dev;
     79        /* - Hub Interface to PCI Bridge Registers - */
     80        /* 12-Clock Retry Enable */
     81        pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
     82        /* Master Latency Timer Count */
     83        pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
     84        /* I/O Address Base */
     85        pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
    8286
    83         /* Set the ac97 audio device staticly. */
    84         dev = PCI_DEV(0x0, 0x1f, 0x5);
    85 
    86         /* Enable access to the IO space. */
    87         pci_write_config8(dev, 0x41, 0x01);
     87        /* - LPC Interface Bridge Registers - */
     88        /* Delayed Transaction Enable */
     89        pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
     90        /* Disable the TCO Timer system reboot feature */
     91        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
     92        /* CPU Frequency Strap */
     93        pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
     94        /* ACPI base address and enable Resource Indicator */
     95        pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
     96        /* Enable the SMBUS */
     97        enable_smbus();
     98        /* ACPI base address and disable Resource Indicator */
     99        pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
     100        /*  ACPI Enable */
     101        pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
    88102}
    89103
     
    103117                }
    104118
     119        /* Set southbridge and superio gpios */
     120        mb_gpio_init();
     121
    105122        smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
    106         mb_gpio_init();
    107123        uart_init();
    108124        console_init();
    109 
    110         enable_smbus();
    111 
    112         /* Prevent the TCO timer from rebooting us */
    113         i82801xx_halt_tco_timer();
    114125
    115126        /* Halt if there was a built in self test failure. */
    116127        report_bist_failure(bist);
    117128
     129        /* Setup mainboard specific registers */
     130        mb_early_setup();
     131
     132        /* SDRAM init */
    118133        sdram_set_registers(memctrl);
    119134        sdram_set_spd_registers(memctrl);
     
    123138        /* ram_check(0, 640 * 1024); */
    124139        /* ram_check(64512 * 1024, 65536 * 1024); */
    125 
    126         ac97_io_enable();
    127140}
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