Changeset 4394

trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c

r3943	r4394
63	63	}
64	64
	65	static void sc520_read_resources(device_t dev)
	66	{
	67	struct resource* res;
	68
	69	pci_dev_read_resources(dev);
	70
	71	res = new_resource(dev, 1);
	72	res->base = 0x0UL;
	73	res->size = 0x400UL;
	74	res->limit = 0xffffUL;
	75	res->flags = IORESOURCE_IO \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	76
	77	res = new_resource(dev, 3); /* IOAPIC */
	78	res->base = 0xfec00000;
	79	res->size = 0x00001000;
	80	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	81	}
	82
65	83
66	84	static struct device_operations cpu_operations = {
67		.read_resources = ~~pci_dev~~_read_resources,
	85	.read_resources = sc520_read_resources,
68	86	.set_resources = pci_dev_set_resources,
69	87	.enable_resources = sc520_enable_resources,
…	…
78	96	.device = 0x3000
79	97	};
80
81
82
83		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
84
85		~~static void pci_domain_read_resources(device_t dev)~~
86		{
87		~~struct resource *resource;~~
88		~~printk_spew("%s\n", __func__);~~
89		~~/* Initialize the system wide io space constraints */~~
90		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
91		~~resource->limit = 0xffffUL;~~
92		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
93
94		~~/* Initialize the system wide memory resources constraints */~~
95		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
96		~~resource->limit = 0xffffffffULL;~~
97		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
98		}
99	98
100	99	static void ram_resource(device_t dev, unsigned long index,
…	…
185	184	}
186	185
187		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
188		{
189		~~printk_spew("%s\n", __func__);~~
190		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
191		~~return max;~~
192		}
193
194
195	186	#if 0
196	187	void sc520_enable_resources(device_t dev) {
…	…
220	211	* function the whole thing will hang in an endless loop on
221	212	* the ts5300. If this is really needed on another platform,
222		* something is concept~~ion~~ally wrong.
	213	* something is conceptually wrong.
223	214	*/
224	215	.enable_resources = 0, //enable_resources,

trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c

r4381	r4394
9	9	#include "chip.h"
10	10	#include "northbridge.h"
11
12		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
13
14		~~static void pci_domain_read_resources(device_t dev)~~
15		{
16		~~struct resource *resource;~~
17
18		~~/* Initialize the system wide io space constraints */~~
19		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
20		~~resource->limit = 0xffffUL;~~
21		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
22
23		~~/* Initialize the system wide memory resources constraints */~~
24		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
25		~~resource->limit = 0xffffffffULL;~~
26		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
27		}
28	11
29	12	static void ram_resource(device_t dev, unsigned long index,
…	…
71	54	#endif
72	55
73		static void pci_domain_set_resources(device_t dev)
	56	static void cpu_pci_domain_set_resources(device_t dev)
74	57	{
75	58	static const uint8_t ramregs[] = {
…	…
128	111	}
129	112
130		static ~~unsigned int pci_domain_scan_bus(device_t dev, unsigned int max~~)
	113	static void cpu_pci_domain_read_resources(struct device *dev)
131	114	{
132		max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
133		return max;
	115	struct resource *res;
	116
	117	pci_domain_read_resources(dev);
	118
	119	/* Reserve space for the IOAPIC. This should be in the Southbridge,
	120	* but I couldn't tell which device to put it in. */
	121	res = new_resource(dev, 2);
	122	res->base = 0xfec00000UL;
	123	res->size = 0x100000UL;
	124	res->limit = 0xffffffffUL;
	125	res->flags = IORESOURCE_MEM \| IORESOURCE_FIXED \| IORESOURCE_STORED \|
	126	IORESOURCE_ASSIGNED;
	127
	128	/* Reserve space for the LAPIC. There's one in every processor, but
	129	* the space only needs to be reserved once, so we do it here. */
	130	res = new_resource(dev, 3);
	131	res->base = 0xfee00000UL;
	132	res->size = 0x10000UL;
	133	res->limit = 0xffffffffUL;
	134	res->flags = IORESOURCE_MEM \| IORESOURCE_FIXED \| IORESOURCE_STORED \|
	135	IORESOURCE_ASSIGNED;
134	136	}
135	137
136	138	static struct device_operations pci_domain_ops = {
137		.read_resources = pci_domain_read_resources,
138		.set_resources = pci_domain_set_resources,
	139	.read_resources = cpu_pci_domain_read_resources,
	140	.set_resources = cpu_pci_domain_set_resources,
139	141	.enable_resources = enable_childrens_resources,
140	142	.init = 0,

trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c

r4381	r4394
7	7	#include <device/pci_ids.h>
8	8	#include <console/console.h>
9
10		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
11		{
12		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
13		~~return max;~~
14		}
15
16		~~static void pci_domain_read_resources(device_t dev)~~
17		{
18		~~struct resource *resource;~~
19
20		~~/* Initialize the system wide io space constraints */~~
21		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
22		~~resource->limit = 0xffffUL;~~
23		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
24
25		~~/* Initialize the system wide memory resources constraints */~~
26		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
27		~~resource->limit = 0xffffffffULL;~~
28		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
29		}
30	9
31	10	static void ram_resource(device_t dev, unsigned long index,

trunk/coreboot-v2/src/devices/cardbus_device.c

r3052	r4394
78	78	if (resource) {
79	79	min_size = resource->size;
80		~~compute_allocate_resource(&dev->link[0], resource,~~
81		~~resource->flags, resource->flags);~~
82	80	/* Allways allocate at least the miniumum size to a
83	81	* cardbus bridge in case a new card is plugged in.

trunk/coreboot-v2/src/devices/device.c

r4271	r4394
13	13	* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
14	14	* Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org>
	15	* Copyright (C) 2009 Myles Watson <mylesgw@gmail.com>
15	16	*/
16	17
…	…
44	45	extern struct device **last_dev_p;
45	46
46		~~/** The upper limit of MEM resource of the devices.~~
47		* Reserve 20M for the system */
48		~~#define DEVICE_MEM_HIGH 0xFEBFFFFFUL~~
49		~~/** The lower limit of IO resource of the devices.~~
50		* Reserve 4k for ISA/Legacy devices */
51		~~#define DEVICE_IO_START 0x1000~~
52	47
53	48	/**
…	…
72	67	spin_lock(&dev_lock);
73	68
74		/* Find the last child of our parent */
75		for~~(child = parent->children; child && child->sibling;~~ ) {
	69	/* Find the last child of our parent. */
	70	for (child = parent->children; child && child->sibling; /* */ ) {
76	71	child = child->sibling;
77	72	}
78	73
79	74	dev = malloc(sizeof(*dev));
80		if (dev == 0) {
	75	if (dev == 0)
81	76	die("DEV: out of memory.\n");
82		}
	77
83	78	memset(dev, 0, sizeof(*dev));
84	79	memcpy(&dev->path, path, sizeof(*path));
85	80
86		/* Initialize the back pointers in the link fields */
87		for(link = 0; link < MAX_LINKS; link++) {
88		dev->link[link].dev = dev;
	81	/* Initialize the back pointers in the link fields. */
	82	for (link = 0; link < MAX_LINKS; link++) {
	83	dev->link[link].dev = dev;
89	84	dev->link[link].link = link;
90	85	}
91	86
92		/* By default devices are enabled */
	87	/* By default devices are enabled. */
93	88	dev->enabled = 1;
94	89
…	…
133	128	struct device *curdev;
134	129
135		printk_spew("%s read_resources bus %d link: %d\n",
136		dev_path(bus->dev), bus->secondary, bus->link);
137
138		/* Walk through all of the devices and find which resources they need. */
139		for(curdev = bus->children; curdev; curdev = curdev->sibling) {
140		unsigned links;
	130	printk_spew("%s %s bus %x link: %d\n", dev_path(bus->dev), __func__,
	131	bus->secondary, bus->link);
	132
	133	/* Walk through all devices and find which resources they need. */
	134	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
141	135	int i;
142		~~if (curdev->have_resources) {~~
143		~~continue;~~
144		}
145	136	if (!curdev->enabled) {
146	137	continue;
…	…
148	139	if (!curdev->ops \|\| !curdev->ops->read_resources) {
149	140	printk_err("%s missing read_resources\n",
150		dev_path(curdev));
	141	dev_path(curdev));
151	142	continue;
152	143	}
153	144	curdev->ops->read_resources(curdev);
154		curdev->have_resources = 1;
155		/* Read in subtractive resources behind the current device */
156		links = 0;
157		for(i = 0; i < curdev->resources; i++) {
158		struct resource *resource;
159		unsigned link;
160		resource = &curdev->resource[i];
161		if (!(resource->flags & IORESOURCE_SUBTRACTIVE))
162		continue;
163		link = IOINDEX_SUBTRACTIVE_LINK(resource->index);
164		if (link > MAX_LINKS) {
165		printk_err("%s subtractive index on link: %d\n",
166		dev_path(curdev), link);
167		continue;
168		}
169		if (!(links & (1 << link))) {
170		links \|= (1 << link);
171		read_resources(&curdev->link[link]);
172		}
173		}
	145
	146	/* Read in the resources behind the current device's links. */
	147	for (i = 0; i < curdev->links; i++)
	148	read_resources(&curdev->link[i]);
174	149	}
175	150	printk_spew("%s read_resources bus %d link: %d done\n",
176		dev_path(bus->dev), bus->secondary, bus->link);
	151	dev_path(bus->dev), bus->secondary, bus->link);
177	152	}
178	153
179	154	struct pick_largest_state {
180	155	struct resource *last;
181		struct device *result_dev;
	156	struct device *result_dev;
182	157	struct resource *result;
183	158	int seen_last;
184	159	};
185	160
186		static void pick_largest_resource(void *gp,
187		~~struct device dev,~~ struct resource resource)
	161	static void pick_largest_resource(void gp, struct device dev,
	162	struct resource *resource)
188	163	{
189	164	struct pick_largest_state *state = gp;
190	165	struct resource *last;
	166
191	167	last = state->last;
192		/* Be certain to pick the successor to last */
	168
	169	/* Be certain to pick the successor to last. */
193	170	if (resource == last) {
194	171	state->seen_last = 1;
…	…
207	184	(state->result->align < resource->align) \|\|
208	185	((state->result->align == resource->align) &&
209		(state->result->size < resource->size)))
210		{
	186	(state->result->size < resource->size))) {
211	187	state->result_dev = dev;
212	188	state->result = resource;
…	…
214	190	}
215	191
216		static struct device largest_resource(struct bus bus, struct resource **result_res,
217		unsigned long type_mask, unsigned long type)
	192	static struct device largest_resource(struct bus bus,
	193	struct resource **result_res,
	194	unsigned long type_mask,
	195	unsigned long type)
218	196	{
219	197	struct pick_largest_state state;
220	198
221	199	state.last = *result_res;
222		state.result_dev = 0;
223		state.result = 0;
	200	state.result_dev = NULL;
	201	state.result = NULL;
224	202	state.seen_last = 0;
225	203
…	…
234	212	*
235	213	* The problem.
236		* - Allocate resources locations for every device.
	214	* - Allocate resource locations for every device.
237	215	* - Don't overlap, and follow the rules of bridges.
238	216	* - Don't overlap with resources in fixed locations.
…	…
241	219	* The strategy.
242	220	* - Devices that have fixed addresses are the minority so don't
243		* worry about them too much. Instead only use part of the address
244		* space for devices with programmable addresses. This easily handles
	221	* worry about them too much. Instead only use part of the address
	222	* space for devices with programmable addresses. This easily handles
245	223	* everything except bridges.
246	224	*
247		* - PCI devices are required to have thier sizes and their alignments
248		* equal. In this case an optimal solution to the packing problem
249		* exists. Allocate all devices from highest alignment to least
250		* alignment or vice versa. Use this.
251		*
252		* - So we can handle more than PCI run two allocation passes on
253		* bridges. The first to see how large the resources are behind
254		* the bridge, and what their alignment requirements are. The
255		* second to assign a safe address to the devices behind the
256		* bridge. This allows me to treat a bridge as just a device with
257		* a couple of resources, and not need to special case it in the
258		* allocator. Also this allows handling of other types of bridges.
259		*
260		*/
261
262		void compute_allocate_resource(
263		struct bus *bus,
264		struct resource *bridge,
265		unsigned long type_mask,
266		unsigned long type)
	225	* - PCI devices are required to have their sizes and their alignments
	226	* equal. In this case an optimal solution to the packing problem
	227	* exists. Allocate all devices from highest alignment to least
	228	* alignment or vice versa. Use this.
	229	*
	230	* - So we can handle more than PCI run two allocation passes on bridges. The
	231	* first to see how large the resources are behind the bridge, and what
	232	* their alignment requirements are. The second to assign a safe address to
	233	* the devices behind the bridge. This allows us to treat a bridge as just
	234	* a device with a couple of resources, and not need to special case it in
	235	* the allocator. Also this allows handling of other types of bridges.
	236	*
	237	*/
	238	void compute_resources(struct bus bus, struct resource bridge,
	239	unsigned long type_mask, unsigned long type)
267	240	{
268	241	struct device *dev;
269	242	struct resource *resource;
270	243	resource_t base;
271		unsigned long align, min_align;
272		min_align = 0;
273		base = bridge->base;
274
275		printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d\n",
276		dev_path(bus->dev),
277		(bridge->flags & IORESOURCE_IO)? "io":
278		(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
279		base, bridge->size, bridge->align, bridge->gran);
280
281		/* We want different minimum alignments for different kinds of
282		* resources. These minimums are not device type specific
283		* but resource type specific.
	244	base = round(bridge->base, bridge->align);
	245
	246	printk_spew( "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx\n",
	247	dev_path(bus->dev), __func__,
	248	(type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
	249	"prefmem" : "mem",
	250	base, bridge->size, bridge->align, bridge->gran, bridge->limit);
	251
	252	/* For each child which is a bridge, compute_resource_needs. */
	253	for (dev = bus->children; dev; dev = dev->sibling) {
	254	unsigned i;
	255	struct resource *child_bridge;
	256
	257	if (!dev->links)
	258	continue;
	259
	260	/* Find the resources with matching type flags. */
	261	for (i = 0; i < dev->resources; i++) {
	262	unsigned link;
	263	child_bridge = &dev->resource[i];
	264
	265	if (!(child_bridge->flags & IORESOURCE_BRIDGE) \|\|
	266	(child_bridge->flags & type_mask) != type)
	267	continue;
	268
	269	/* Split prefetchable memory if combined. Many domains
	270	* use the same address space for prefetchable memory
	271	* and non-prefetchable memory. Bridges below them
	272	* need it separated. Add the PREFETCH flag to the
	273	* type_mask and type.
	274	*/
	275	link = IOINDEX_LINK(child_bridge->index);
	276	compute_resources(&dev->link[link], child_bridge,
	277	type_mask \| IORESOURCE_PREFETCH,
	278	type \| (child_bridge->flags &
	279	IORESOURCE_PREFETCH));
	280	}
	281	}
	282
	283	/* Remember we haven't found anything yet. */
	284	resource = NULL;
	285
	286	/* Walk through all the resources on the current bus and compute the
	287	* amount of address space taken by them. Take granularity and
	288	* alignment into account.
284	289	*/
285		if (bridge->flags & IORESOURCE_IO) {
286		min_align = log2(DEVICE_IO_ALIGN);
287		}
288		if (bridge->flags & IORESOURCE_MEM) {
289		min_align = log2(DEVICE_MEM_ALIGN);
290		}
291
292		/* Make certain I have read in all of the resources */
293		read_resources(bus);
294
295		/* Remember I haven't found anything yet. */
296		resource = 0;
297
298		/* Walk through all the devices on the current bus and
299		* compute the addresses.
300		*/
301		while((dev = largest_resource(bus, &resource, type_mask, type))) {
302		resource_t size;
303		/* Do NOT I repeat do not ignore resources which have zero size.
304		* If they need to be ignored dev->read_resources should not even
305		* return them. Some resources must be set even when they have
306		* no size. PCI bridge resources are a good example of this.
307		*/
308		/* Make certain we are dealing with a good minimum size */
309		size = resource->size;
310		align = resource->align;
311		if (align < min_align) {
312		align = min_align;
313		}
314
315		/* Propagate the resource alignment to the bridge register */
316		if (align > bridge->align) {
317		bridge->align = align;
318		}
319
320		if (resource->flags & IORESOURCE_FIXED) {
321		continue;
322		}
323
324		/* Propogate the resource limit to the bridge register */
	290	while ((dev = largest_resource(bus, &resource, type_mask, type))) {
	291
	292	/* Size 0 resources can be skipped. */
	293	if (!resource->size) {
	294	continue;
	295	}
	296
	297	/* Propagate the resource alignment to the bridge resource. */
	298	if (resource->align > bridge->align) {
	299	bridge->align = resource->align;
	300	}
	301
	302	/* Propagate the resource limit to the bridge register. */
325	303	if (bridge->limit > resource->limit) {
326	304	bridge->limit = resource->limit;
327	305	}
328		#warning This heuristic should be replaced by real devices with fixed resources.
329		/* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */
330		if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) {
331		bridge->limit = DEVICE_MEM_HIGH;
	306
	307	/* Warn if it looks like APICs aren't declared. */
	308	if ((resource->limit == 0xffffffff) &&
	309	(resource->flags & IORESOURCE_ASSIGNED)) {
	310	printk_err("Resource limit looks wrong! (no APIC?)\n");
	311	printk_err("%s %02lx limit %08Lx\n", dev_path(dev),
	312	resource->index, resource->limit);
332	313	}
333	314
334	315	if (resource->flags & IORESOURCE_IO) {
335		/* Don't allow potential aliases over the
336		* legacy pci expansion card addresses.
337		* The legacy pci decodes only 10 bits,
338		* uses 100h - 3ffh. Therefor, only 0 - ff
339		* can be used out of each 400h block of io
340		* space.
	316	/* Don't allow potential aliases over the legacy PCI
	317	* expansion card addresses. The legacy PCI decodes
	318	* only 10 bits, uses 0x100 - 0x3ff. Therefore, only
	319	* 0x00 - 0xff can be used out of each 0x400 block of
	320	* I/O space.
341	321	*/
342	322	if ((base & 0x300) != 0) {
343	323	base = (base & ~0x3ff) + 0x400;
344	324	}
345		/* Don't allow allocations in the VGA IO range.
	325	/* Don't allow allocations in the VGA I/O range.
346	326	* PCI has special cases for that.
347	327	*/
…	…
350	330	}
351	331	}
352		if (((round(base, align) + size) -1) <= resource->limit) {
353		/* base must be aligned to size */
354		base = round(base, align);
355		resource->base = base;
356		resource->flags \|= IORESOURCE_ASSIGNED;
357		resource->flags &= ~IORESOURCE_STORED;
358		base += size;
359
360		printk_spew("%s %02lx * [0x%08Lx - 0x%08Lx] %s\n",
361		dev_path(dev),
362		resource->index,
363		resource->base,
364		resource->base + resource->size - 1,
365		(resource->flags & IORESOURCE_IO)? "io":
366		(resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
367		}
368		#if CONFIG_PCIE_CONFIGSPACE_HOLE
369		#warning Handle PCIe hole differently...
370		if (base >= 0xf0000000 && base < 0xf4000000) {
371		base = 0xf4000000;
372		}
373		#endif
	332	/* Base must be aligned. */
	333	base = round(base, resource->align);
	334	resource->base = base;
	335	base += resource->size;
	336
	337	printk_spew("%s %02lx * [0x%llx - 0x%llx] %s\n",
	338	dev_path(dev), resource->index,
	339	resource->base,
	340	resource->base + resource->size - 1,
	341	(resource->flags & IORESOURCE_IO) ? "io" :
	342	(resource->flags & IORESOURCE_PREFETCH) ?
	343	"prefmem" : "mem");
374	344	}
375	345	/* A pci bridge resource does not need to be a power
…	…
379	349	* decoded by the bridge.
380	350	*/
381		bridge->size = round(base, bridge->gran) - bridge->base;
382
383		printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d done\n",
384		dev_path(bus->dev),
385		(bridge->flags & IORESOURCE_IO)? "io":
386		(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem",
387		base, bridge->size, bridge->align, bridge->gran);
	351	bridge->size = round(base, bridge->gran) -
	352	round(bridge->base, bridge->align);
	353
	354	printk_spew("%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n",
	355	dev_path(bus->dev), __func__,
	356	(bridge->flags & IORESOURCE_IO) ? "io" :
	357	(bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem",
	358	base, bridge->size, bridge->align, bridge->gran, bridge->limit);
	359	}
	360
	361	/**
	362	* This function is the second part of the resource allocator.
	363	*
	364	* The problem.
	365	* - Allocate resource locations for every device.
	366	* - Don't overlap, and follow the rules of bridges.
	367	* - Don't overlap with resources in fixed locations.
	368	* - Be efficient so we don't have ugly strategies.
	369	*
	370	* The strategy.
	371	* - Devices that have fixed addresses are the minority so don't
	372	* worry about them too much. Instead only use part of the address
	373	* space for devices with programmable addresses. This easily handles
	374	* everything except bridges.
	375	*
	376	* - PCI devices are required to have their sizes and their alignments
	377	* equal. In this case an optimal solution to the packing problem
	378	* exists. Allocate all devices from highest alignment to least
	379	* alignment or vice versa. Use this.
	380	*
	381	* - So we can handle more than PCI run two allocation passes on bridges. The
	382	* first to see how large the resources are behind the bridge, and what
	383	* their alignment requirements are. The second to assign a safe address to
	384	* the devices behind the bridge. This allows us to treat a bridge as just
	385	* a device with a couple of resources, and not need to special case it in
	386	* the allocator. Also this allows handling of other types of bridges.
	387	*
	388	* - This function assigns the resources a value.
	389	*
	390	* @param bus The bus we are traversing.
	391	* @param bridge The bridge resource which must contain the bus' resources.
	392	* @param type_mask This value gets anded with the resource type.
	393	* @param type This value must match the result of the and.
	394	*/
	395	void allocate_resources(struct bus bus, struct resource bridge,
	396	unsigned long type_mask, unsigned long type)
	397	{
	398	struct device *dev;
	399	struct resource *resource;
	400	resource_t base;
	401	base = bridge->base;
	402
	403	printk_spew("%s %s_%s: base:%llx size:%llx align:%d gran:%d limit:%llx\n",
	404	dev_path(bus->dev), __func__,
	405	(type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
	406	"prefmem" : "mem",
	407	base, bridge->size, bridge->align, bridge->gran, bridge->limit);
	408
	409	/* Remember we haven't found anything yet. */
	410	resource = NULL;
	411
	412	/* Walk through all the resources on the current bus and allocate them
	413	* address space.
	414	*/
	415	while ((dev = largest_resource(bus, &resource, type_mask, type))) {
	416
	417	/* Propagate the bridge limit to the resource register. */
	418	if (resource->limit > bridge->limit) {
	419	resource->limit = bridge->limit;
	420	}
	421
	422	/* Size 0 resources can be skipped. */
	423	if (!resource->size) {
	424	/* Set the base to limit so it doesn't confuse tolm. */
	425	resource->base = resource->limit;
	426	resource->flags \|= IORESOURCE_ASSIGNED;
	427	continue;
	428	}
	429
	430	if (resource->flags & IORESOURCE_IO) {
	431	/* Don't allow potential aliases over the legacy PCI
	432	* expansion card addresses. The legacy PCI decodes
	433	* only 10 bits, uses 0x100 - 0x3ff. Therefore, only
	434	* 0x00 - 0xff can be used out of each 0x400 block of
	435	* I/O space.
	436	*/
	437	if ((base & 0x300) != 0) {
	438	base = (base & ~0x3ff) + 0x400;
	439	}
	440	/* Don't allow allocations in the VGA I/O range.
	441	* PCI has special cases for that.
	442	*/
	443	else if ((base >= 0x3b0) && (base <= 0x3df)) {
	444	base = 0x3e0;
	445	}
	446	}
	447
	448	if ((round(base, resource->align) + resource->size - 1) <=
	449	resource->limit) {
	450	/* Base must be aligned. */
	451	base = round(base, resource->align);
	452	resource->base = base;
	453	resource->flags \|= IORESOURCE_ASSIGNED;
	454	resource->flags &= ~IORESOURCE_STORED;
	455	base += resource->size;
	456	} else {
	457	printk_err("!! Resource didn't fit !!\n");
	458	printk_err(" aligned base %llx size %llx limit %llx\n",
	459	round(base, resource->align), resource->size,
	460	resource->limit);
	461	printk_err(" %llx needs to be <= %llx (limit)\n",
	462	(round(base, resource->align) +
	463	resource->size) - 1, resource->limit);
	464	printk_err(" %s%s %02lx * [0x%llx - 0x%llx] %s\n",
	465	(resource->
	466	flags & IORESOURCE_ASSIGNED) ? "Assigned: " :
	467	"", dev_path(dev), resource->index,
	468	resource->base,
	469	resource->base + resource->size - 1,
	470	(resource->
	471	flags & IORESOURCE_IO) ? "io" : (resource->
	472	flags &
	473	IORESOURCE_PREFETCH)
	474	? "prefmem" : "mem");
	475	}
	476
	477	printk_spew("%s%s %02lx * [0x%llx - 0x%llx] %s\n",
	478	(resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: "
	479	: "",
	480	dev_path(dev), resource->index, resource->base,
	481	resource->size ? resource->base + resource->size - 1 :
	482	resource->base,
	483	(resource->flags & IORESOURCE_IO) ? "io" :
	484	(resource->flags & IORESOURCE_PREFETCH) ? "prefmem" :
	485	"mem");
	486	}
	487	/* A PCI bridge resource does not need to be a power of two size, but
	488	* it does have a minimum granularity. Round the size up to that
	489	* minimum granularity so we know not to place something else at an
	490	* address positively decoded by the bridge.
	491	*/
	492
	493	bridge->flags \|= IORESOURCE_ASSIGNED;
	494
	495	printk_spew("%s %s_%s: next_base: %llx size: %llx align: %d gran: %d done\n",
	496	dev_path(bus->dev), __func__,
	497	(type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
	498	"prefmem" : "mem",
	499	base, bridge->size, bridge->align, bridge->gran);
	500
	501	/* For each child which is a bridge, allocate_resources. */
	502	for (dev = bus->children; dev; dev = dev->sibling) {
	503	unsigned i;
	504	struct resource *child_bridge;
	505
	506	if (!dev->links)
	507	continue;
	508
	509	/* Find the resources with matching type flags. */
	510	for (i = 0; i < dev->resources; i++) {
	511	unsigned link;
	512	child_bridge = &dev->resource[i];
	513
	514	if (!(child_bridge->flags & IORESOURCE_BRIDGE) \|\|
	515	(child_bridge->flags & type_mask) != type)
	516	continue;
	517
	518	/* Split prefetchable memory if combined. Many domains
	519	* use the same address space for prefetchable memory
	520	* and non-prefetchable memory. Bridges below them
	521	* need it separated. Add the PREFETCH flag to the
	522	* type_mask and type.
	523	*/
	524	link = IOINDEX_LINK(child_bridge->index);
	525	allocate_resources(&dev->link[link], child_bridge,
	526	type_mask \| IORESOURCE_PREFETCH,
	527	type \| (child_bridge->flags &
	528	IORESOURCE_PREFETCH));
	529	}
	530	}
	531	}
	532
	533	#if CONFIG_PCI_64BIT_PREF_MEM == 1
	534	#define MEM_MASK (IORESOURCE_PREFETCH \| IORESOURCE_MEM)
	535	#else
	536	#define MEM_MASK (IORESOURCE_MEM)
	537	#endif
	538	#define IO_MASK (IORESOURCE_IO)
	539	#define PREF_TYPE (IORESOURCE_PREFETCH \| IORESOURCE_MEM)
	540	#define MEM_TYPE (IORESOURCE_MEM)
	541	#define IO_TYPE (IORESOURCE_IO)
	542
	543	struct constraints {
	544	struct resource pref, io, mem;
	545	};
	546
	547	static void constrain_resources(struct device dev, struct constraints limits)
	548	{
	549	struct device *child;
	550	struct resource *res;
	551	struct resource *lim;
	552	int i;
	553
	554	printk_spew("%s: %s\n", __func__, dev_path(dev));
	555
	556	/* Constrain limits based on the fixed resources of this device. */
	557	for (i = 0; i < dev->resources; i++) {
	558	res = &dev->resource[i];
	559	if (!(res->flags & IORESOURCE_FIXED))
	560	continue;
	561
	562	/* PREFETCH, MEM, or I/O - skip any others. */
	563	if ((res->flags & MEM_MASK) == PREF_TYPE)
	564	lim = &limits->pref;
	565	else if ((res->flags & MEM_MASK) == MEM_TYPE)
	566	lim = &limits->mem;
	567	else if ((res->flags & IO_MASK) == IO_TYPE)
	568	lim = &limits->io;
	569	else
	570	continue;
	571
	572	/* Is it already outside the limits? */
	573	if (res->size && (((res->base + res->size -1) < lim->base) \|\|
	574	(res->base > lim->limit)))
	575	continue;
	576
	577	/* Choose to be above or below fixed resources. This
	578	* check is signed so that "negative" amounts of space
	579	* are handled correctly.
	580	*/
	581	if ((signed long long)(lim->limit - (res->base + res->size -1)) >
	582	(signed long long)(res->base - lim->base))
	583	lim->base = res->base + res->size;
	584	else
	585	lim->limit = res->base -1;
	586	}
	587
	588	/* Descend into every enabled child and look for fixed resources. */
	589	for (i = 0; i < dev->links; i++)
	590	for (child = dev->link[i].children; child;
	591	child = child->sibling)
	592	if (child->enabled)
	593	constrain_resources(child, limits);
	594	}
	595
	596	static void avoid_fixed_resources(struct device *dev)
	597	{
	598	struct constraints limits;
	599	struct resource *res;
	600	int i;
	601
	602	printk_spew("%s: %s\n", __func__, dev_path(dev));
	603	/* Initialize constraints to maximum size. */
	604
	605	limits.pref.base = 0;
	606	limits.pref.limit = 0xffffffffffffffffULL;
	607	limits.io.base = 0;
	608	limits.io.limit = 0xffffffffffffffffULL;
	609	limits.mem.base = 0;
	610	limits.mem.limit = 0xffffffffffffffffULL;
	611
	612	/* Constrain the limits to dev's initial resources. */
	613	for (i = 0; i < dev->resources; i++) {
	614	res = &dev->resource[i];
	615	if ((res->flags & IORESOURCE_FIXED))
	616	continue;
	617	printk_spew("%s:@%s %02lx limit %08Lx\n", __func__,
	618	dev_path(dev), res->index, res->limit);
	619	if ((res->flags & MEM_MASK) == PREF_TYPE &&
	620	(res->limit < limits.pref.limit))
	621	limits.pref.limit = res->limit;
	622	if ((res->flags & MEM_MASK) == MEM_TYPE &&
	623	(res->limit < limits.mem.limit))
	624	limits.mem.limit = res->limit;
	625	if ((res->flags & IO_MASK) == IO_TYPE &&
	626	(res->limit < limits.io.limit))
	627	limits.io.limit = res->limit;
	628	}
	629
	630	/* Look through the tree for fixed resources and update the limits. */
	631	constrain_resources(dev, &limits);
	632
	633	/* Update dev's resources with new limits. */
	634	for (i = 0; i < dev->resources; i++) {
	635	struct resource *lim;
	636	res = &dev->resource[i];
	637
	638	if ((res->flags & IORESOURCE_FIXED))
	639	continue;
	640
	641	/* PREFETCH, MEM, or I/O - skip any others. */
	642	if ((res->flags & MEM_MASK) == PREF_TYPE)
	643	lim = &limits.pref;
	644	else if ((res->flags & MEM_MASK) == MEM_TYPE)
	645	lim = &limits.mem;
	646	else if ((res->flags & IO_MASK) == IO_TYPE)
	647	lim = &limits.io;
	648	else
	649	continue;
	650
	651	printk_spew("%s2: %s@%02lx limit %08Lx\n", __func__,
	652	dev_path(dev), res->index, res->limit);
	653	printk_spew("\tlim->base %08Lx lim->limit %08Lx\n",
	654	lim->base, lim->limit);
	655
	656	/* Is the resource outside the limits? */
	657	if (lim->base > res->base)
	658	res->base = lim->base;
	659	if (res->limit > lim->limit)
	660	res->limit = lim->limit;
	661	}
388	662	}
389	663
…	…
393	667	{
394	668	#warning "FIXME modify allocate_vga_resource so it is less pci centric!"
395		#warning "This function knows to ~~much about PCI stuff, it should be just a iet~~rator/visitor."
396
397		/* FIXME ~~handle the VGA pallette snooping~~ */
	669	#warning "This function knows too much about PCI stuff, it should be just a iterator/visitor."
	670
	671	/* FIXME: Handle the VGA palette snooping. */
398	672	struct device dev, vga, vga_onboard, vga_first, *vga_last;
399	673	struct bus *bus;
…	…
403	677	vga_first = 0;
404	678	vga_last = 0;
405		for(dev = all_devices; dev; dev = dev->next) {
406		if (!dev->enabled) continue;
	679	for (dev = all_devices; dev; dev = dev->next) {
	680	if (!dev->enabled)
	681	continue;
407	682	if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
408		((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER))
409		{
410		if (!vga_first) {
411		if (dev->on_mainboard) {
412		vga_onboard = dev;
413		} else {
414		vga_first = dev;
415		}
416		} else {
417		if (dev->on_mainboard) {
418		vga_onboard = dev;
419		} else {
420		vga_last = dev;
421		}
422		}
423
424		/* It isn't safe to enable other VGA cards */
	683	((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
	684	if (!vga_first) {
	685	if (dev->on_mainboard) {
	686	vga_onboard = dev;
	687	} else {
	688	vga_first = dev;
	689	}
	690	} else {
	691	if (dev->on_mainboard) {
	692	vga_onboard = dev;
	693	} else {
	694	vga_last = dev;
	695	}
	696	}
	697
	698	/* It isn't safe to enable other VGA cards. */
425	699	dev->command &= ~(PCI_COMMAND_MEMORY \| PCI_COMMAND_IO);
426	700	}
427	701	}
428	702
429		vga = vga_last;
430
431		if(!vga) {
432		vga = vga_first;
433		}
434
	703	vga = vga_last;
	704
	705	if (!vga) {
	706	vga = vga_first;
	707	}
435	708	#if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1
436		if (vga_onboard) // will use on board vga as pri
	709	if (vga_onboard) // Will use on board VGA as pri.
437	710	#else
438		if (!vga) // will use last add on adapter as pri
	711	if (!vga) // Will use last add on adapter as pri.
439	712	#endif
440		{
441		vga = vga_onboard;
442		}
443
	713	{
	714	vga = vga_onboard;
	715	}
444	716
445	717	if (vga) {
446		/* ~~vga is first add on card or the only onboard vga~~ */
	718	/* VGA is first add on card or the only onboard VGA. */
447	719	printk_debug("Allocating VGA resource %s\n", dev_path(vga));
448		/* All legacy VGA cards have MEM & I/O space registers */
	720	/* All legacy VGA cards have MEM & I/O space registers. */
449	721	vga->command \|= (PCI_COMMAND_MEMORY \| PCI_COMMAND_IO);
450	722	vga_pri = vga;
451	723	bus = vga->bus;
452	724	}
453		/* Now walk up the bridges setting the VGA enable */
454		while(bus) {
	725	/* Now walk up the bridges setting the VGA enable. */
	726	while (bus) {
455	727	printk_debug("Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
456	728	dev_path(bus->dev));
457	729	bus->bridge_ctrl \|= PCI_BRIDGE_CTL_VGA;
458		bus = (bus == bus->dev->bus)? 0 : bus->dev->bus;
	730	bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus;
459	731	}
460	732	}
461	733
462	734	#endif
463
464	735
465	736	/**
…	…
481	752
482	753	printk_spew("%s assign_resources, bus %d link: %d\n",
483		dev_path(bus->dev), bus->secondary, bus->link);
484
485		for(curdev = bus->children; curdev; curdev = curdev->sibling) {
	754	dev_path(bus->dev), bus->secondary, bus->link);
	755
	756	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
486	757	if (!curdev->enabled \|\| !curdev->resources) {
487	758	continue;
…	…
489	760	if (!curdev->ops \|\| !curdev->ops->set_resources) {
490	761	printk_err("%s missing set_resources\n",
491		dev_path(curdev));
	762	dev_path(curdev));
492	763	continue;
493	764	}
…	…
495	766	}
496	767	printk_spew("%s assign_resources, bus %d link: %d\n",
497		dev_path(bus->dev), bus->secondary, bus->link);
	768	dev_path(bus->dev), bus->secondary, bus->link);
498	769	}
499	770
…	…
540	811	int reset_bus(struct bus *bus)
541	812	{
542		if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus)
543		{
	813	if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus) {
544	814	bus->dev->ops->reset_bus(bus);
545	815	bus->reset_needed = 0;
…	…
552	822	* @brief Scan for devices on a bus.
553	823	*
554		* If there are bridges on the bus, recursively scan the buses behind the bridges.
555		* If the setting up and tuning of the bus causes a reset to be required,
556		* reset the bus and scan it again.
557		*
558		* @param bus pointer to the bus device
559		* @param max current bus number
560		*
561		* @return The maximum bus number found, after scanning all subordinate busses
562		*/
563		unsigned int scan_bus(device_t bus, unsigned int max)
	824	* If there are bridges on the bus, recursively scan the buses behind the
	825	* bridges. If the setting up and tuning of the bus causes a reset to be
	826	* required, reset the bus and scan it again.
	827	*
	828	* @param busdev Pointer to the bus device.
	829	* @param max Current bus number.
	830	* @return The maximum bus number found, after scanning all subordinate buses.
	831	*/
	832	unsigned int scan_bus(struct device *busdev, unsigned int max)
564	833	{
565	834	unsigned int new_max;
566	835	int do_scan_bus;
567		if ( !bus \|\|
568		!bus->enabled \|\|
569		!bus->ops \|\|
570		!bus->ops->scan_bus)
571		{
	836	if (!busdev \|\| !busdev->enabled \|\| !busdev->ops \|\|
	837	!busdev->ops->scan_bus) {
572	838	return max;
573	839	}
	840
574	841	do_scan_bus = 1;
575		while(do_scan_bus) {
	842	while (do_scan_bus) {
576	843	int link;
577		new_max = bus~~->ops->scan_bus(bus~~, max);
	844	new_max = busdev->ops->scan_bus(busdev, max);
578	845	do_scan_bus = 0;
579		for~~(link = 0; link < bus~~->links; link++) {
580		if (bus->link[link].reset_needed) {
581		if (reset_bus(&bus->link[link])) {
	846	for (link = 0; link < busdev->links; link++) {
	847	if (busdev->link[link].reset_needed) {
	848	if (reset_bus(&busdev->link[link])) {
582	849	do_scan_bus = 1;
583	850	} else {
584		bus->bus->reset_needed = 1;
	851	busdev->bus->reset_needed = 1;
585	852	}
586	853	}
…	…
589	856	return new_max;
590	857	}
591
592	858
593	859	/**
…	…
620	886	root = &dev_root;
621	887
622		show_all_devs(BIOS_DEBUG, "Before ~~Phase 3~~.");
	888	show_all_devs(BIOS_DEBUG, "Before Device Enumeration.");
623	889	printk_debug("Compare with tree...\n");
624	890
…	…
644	910	* relocated to their final position and stored to the hardware.
645	911	*
646		* I/O resources start at DEVICE_IO_START and grow upward. MEM resources start
647		* at DEVICE_MEM_HIGH and grow downward.
	912	* I/O resources grow upward. MEM resources grow downward.
648	913	*
649	914	* Since the assignment is hierarchical we set the values into the dev_root
…	…
652	917	void dev_configure(void)
653	918	{
654		struct resource ~~io, mem~~;
	919	struct resource *res;
655	920	struct device *root;
	921	struct device *child;
	922	int i;
656	923
657	924	printk_info("Allocating resources...\n");
…	…
659	926	root = &dev_root;
660	927
661		print_resource_tree(root, BIOS_DEBUG, "Original.");
662
663		if (!root->ops \|\| !root->ops->read_resources) {
664		printk_err("dev_root missing read_resources\n");
665		return;
666		}
667		if (!root->ops \|\| !root->ops->set_resources) {
668		printk_err("dev_root missing set_resources\n");
669		return;
670		}
	928	/* Each domain should create resources which contain the entire address
	929	* space for IO, MEM, and PREFMEM resources in the domain. The
	930	* allocation of device resources will be done from this address space.
	931	*/
	932
	933	/* Read the resources for the entire tree. */
671	934
672	935	printk_info("Reading resources...\n");
673		r~~oot->ops->read_resources(root~~);
	936	read_resources(&root->link[0]);
674	937	printk_info("Done reading resources.\n");
675	938
676	939	print_resource_tree(root, BIOS_DEBUG, "After reading.");
677	940
678		/* Get the resources */
679		io = &root->resource[0];
680		mem = &root->resource[1];
681		/* Make certain the io devices are allocated somewhere safe. */
682		io->base = DEVICE_IO_START;
683		io->flags \|= IORESOURCE_ASSIGNED;
684		io->flags &= ~IORESOURCE_STORED;
685		/* Now reallocate the pci resources memory with the
686		* highest addresses I can manage.
	941	/* Compute resources for all domains. */
	942	for (child = root->link[0].children; child; child = child->sibling) {
	943	if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
	944	continue;
	945	for (i = 0; i < child->resources; i++) {
	946	res = &child->resource[i];
	947	if (res->flags & IORESOURCE_FIXED)
	948	continue;
	949	if (res->flags & IORESOURCE_PREFETCH) {
	950	compute_resources(&child->link[0],
	951	res, MEM_MASK, PREF_TYPE);
	952	continue;
	953	}
	954	if (res->flags & IORESOURCE_MEM) {
	955	compute_resources(&child->link[0],
	956	res, MEM_MASK, MEM_TYPE);
	957	continue;
	958	}
	959	if (res->flags & IORESOURCE_IO) {
	960	compute_resources(&child->link[0],
	961	res, IO_MASK, IO_TYPE);
	962	continue;
	963	}
	964	}
	965	}
	966
	967	/* For all domains. */
	968	for (child = root->link[0].children; child; child=child->sibling)
	969	if (child->path.type == DEVICE_PATH_PCI_DOMAIN)
	970	avoid_fixed_resources(child);
	971
	972	/* Now we need to adjust the resources. MEM resources need to start at
	973	* the highest address managable.
687	974	*/
688		mem->base = resource_max(&root->resource[1]);
689		mem->flags \|= IORESOURCE_ASSIGNED;
690		mem->flags &= ~IORESOURCE_STORED;
	975	for (child = root->link[0].children; child; child = child->sibling) {
	976	if (child->path.type != DEVICE_PATH_PCI_DOMAIN)
	977	continue;
	978	for (i = 0; i < child->resources; i++) {
	979	res = &child->resource[i];
	980	if (!(res->flags & IORESOURCE_MEM) \|\|
	981	res->flags & IORESOURCE_FIXED)
	982	continue;
	983	res->base = resource_max(res);
	984	}
	985	}
691	986
692	987	#if CONFIG_CONSOLE_VGA == 1
693		/* Allocate the VGA I/O resource.. */
	988	/* Allocate the VGA I/O resource. */
694	989	allocate_vga_resource();
695	990	print_resource_tree(root, BIOS_DEBUG, "After VGA.");
…	…
698	993	/* Store the computed resource allocations into device registers ... */
699	994	printk_info("Setting resources...\n");
700		root->ops->set_resources(root);
	995	for (child = root->link[0].children; child; child = child->sibling) {
	996	if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
	997	continue;
	998	for (i = 0; i < child->resources; i++) {
	999	res = &child->resource[i];
	1000	if (res->flags & IORESOURCE_FIXED)
	1001	continue;
	1002	if (res->flags & IORESOURCE_PREFETCH) {
	1003	allocate_resources(&child->link[0],
	1004	res, MEM_MASK, PREF_TYPE);
	1005	continue;
	1006	}
	1007	if (res->flags & IORESOURCE_MEM) {
	1008	allocate_resources(&child->link[0],
	1009	res, MEM_MASK, MEM_TYPE);
	1010	continue;
	1011	}
	1012	if (res->flags & IORESOURCE_IO) {
	1013	allocate_resources(&child->link[0],
	1014	res, IO_MASK, IO_TYPE);
	1015	continue;
	1016	}
	1017	}
	1018	}
	1019	assign_resources(&root->link[0]);
701	1020	printk_info("Done setting resources.\n");
702		~~#if 0~~
703		~~mem->flags \|= IORESOURCE_STORED;~~
704		~~report_resource_stored(root, mem, "");~~
705		~~#endif~~
706	1021	print_resource_tree(root, BIOS_DEBUG, "After assigning values.");
707	1022
…	…
737	1052
738	1053	printk_info("Initializing devices...\n");
739		for(dev = all_devices; dev; dev = dev->next) {
	1054	for (dev = all_devices; dev; dev = dev->next) {
740	1055	if (dev->enabled && !dev->initialized &&
741		dev->ops && dev->ops->init)
742		{
	1056	dev->ops && dev->ops->init) {
743	1057	if (dev->path.type == DEVICE_PATH_I2C) {
744		printk_debug("smbus: %s[%d]->",
745		dev_path(dev->bus->dev), dev->bus->link);
	1058	printk_debug("smbus: %s[%d]->",
	1059	dev_path(dev->bus->dev),
	1060	dev->bus->link);
746	1061	}
747	1062	printk_debug("%s init\n", dev_path(dev));
…	…
753	1068	show_all_devs(BIOS_DEBUG, "After init.");
754	1069	}
755

trunk/coreboot-v2/src/devices/device_util.c

r4381	r4394
488	488	int i;
489	489	/* Ignore disabled devices */
490		if (!curdev->~~have_resources~~) continue;
	490	if (!curdev->enabled) continue;
491	491	for(i = 0; i < curdev->resources; i++) {
492	492	struct resource *resource = &curdev->resource[i];
…	…
515	515	int i;
516	516	/* Ignore disabled devices */
517		if (!curdev->~~have_resources~~) continue;
	517	if (!curdev->enabled) continue;
518	518	for(i = 0; i < curdev->resources; i++) {
519	519	struct resource *resource = &curdev->resource[i];

trunk/coreboot-v2/src/devices/pci_device.c

r4381	r4394
16	16
17	17	/*
18		* PCI Bus Services, see include/linux/pci.h for further explanation.
19		*
20		* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21		* David Mosberger-Tang
22		*
23		* Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
	18	* PCI Bus Services, see include/linux/pci.h for further explanation.
	19	*
	20	* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
	21	* David Mosberger-Tang
	22	*
	23	* Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
24	24	*/
25	25
…	…
52	52	#endif
53	53
54		u~~int8_t pci_moving_config8(struct device *dev, unsigned~~ reg)
55		{
56		u~~int8_t~~ value, ones, zeroes;
	54	u8 pci_moving_config8(struct device *dev, unsigned int reg)
	55	{
	56	u8 value, ones, zeroes;
57	57	value = pci_read_config8(dev, reg);
58	58
…	…
68	68	}
69	69
70		u~~int16_t pci_moving_config16(struct device *dev, unsigned~~ reg)
71		{
72		u~~int16_t~~ value, ones, zeroes;
	70	u16 pci_moving_config16(struct device * dev, unsigned int reg)
	71	{
	72	u16 value, ones, zeroes;
73	73	value = pci_read_config16(dev, reg);
74	74
…	…
84	84	}
85	85
86		u~~int32_t pci_moving_config32(struct device *dev, unsigned~~ reg)
87		{
88		u~~int32_t~~ value, ones, zeroes;
	86	u32 pci_moving_config32(struct device * dev, unsigned int reg)
	87	{
	88	u32 value, ones, zeroes;
89	89	value = pci_read_config32(dev, reg);
90	90
…	…
100	100	}
101	101
102		unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last)
	102	/**
	103	* Given a device, a capability type, and a last position, return the next
	104	* matching capability. Always start at the head of the list.
	105	*
	106	* @param dev Pointer to the device structure.
	107	* @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
	108	* @param last Location of the PCI capability register to start from.
	109	*/
	110	unsigned pci_find_next_capability(struct device *dev, unsigned cap,
	111	unsigned last)
103	112	{
104	113	unsigned pos;
…	…
110	119	return 0;
111	120	}
112		switch(dev->hdr_type & 0x7f) {
	121	switch (dev->hdr_type & 0x7f) {
113	122	case PCI_HEADER_TYPE_NORMAL:
114	123	case PCI_HEADER_TYPE_BRIDGE:
…	…
122	131	}
123	132	pos = pci_read_config8(dev, pos);
124		while~~(reps-- && (pos >= 0x40)) { /* loop through the linked list~~ */
	133	while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
125	134	int this_cap;
126	135	pos &= ~3;
127	136	this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
128		printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
	137	printk_spew("Capability: type 0x%02x @ 0x%02x\n", this_cap,
	138	pos);
129	139	if (this_cap == 0xff) {
130	140	break;
…	…
141	151	}
142	152
	153	/**
	154	* Given a device, and a capability type, return the next matching
	155	* capability. Always start at the head of the list.
	156	*
	157	* @param dev Pointer to the device structure.
	158	* @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
	159	*/
143	160	unsigned pci_find_capability(device_t dev, unsigned cap)
144	161	{
145	162	return pci_find_next_capability(dev, cap, 0);
146
147		}
148
149		/** Given a device and register, read the size of the BAR for that register.
150		* ~~@param dev Pointer to the device structure~~
151		* @param ~~resource Pointer to the resource structure~~
152		* @param index ~~Address of the pci configuration register~~
	163	}
	164
	165	/**
	166	* Given a device and register, read the size of the BAR for that register.
	167	*
	168	* @param dev Pointer to the device structure.
	169	* @param index Address of the PCI configuration register.
153	170	*/
154	171	struct resource pci_get_resource(struct device dev, unsigned long index)
…	…
156	173	struct resource *resource;
157	174	unsigned long value, attr;
158		resource_t moving, limit;
159
160		/* Initialize the resources to nothing */
	175	resource_t moving, limit;
	176
	177	/* Initialize the resources to nothing. */
161	178	resource = new_resource(dev, index);
162	179
163		/* Get the initial value */
	180	/* Get the initial value. */
164	181	value = pci_read_config32(dev, index);
165	182
166		/* See which bits move */
	183	/* See which bits move. */
167	184	moving = pci_moving_config32(dev, index);
168	185
169		/* Initialize attr to the bits that do not move */
	186	/* Initialize attr to the bits that do not move. */
170	187	attr = value & ~moving;
171	188
172		/* If it is a 64bit resource look at the high half as well */
	189	/* If it is a 64bit resource look at the high half as well. */
173	190	if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
174		((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
175		{
176		/* Find the high bits that move */
177		moving \|= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
	191	((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
	192	PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
	193	/* Find the high bits that move. */
	194	moving \|=
	195	((resource_t) pci_moving_config32(dev, index + 4)) << 32;
178	196	}
179	197	/* Find the resource constraints.
180		*
181	198	* Start by finding the bits that move. From there:
182	199	* - Size is the least significant bit of the bits that move.
183	200	* - Limit is all of the bits that move plus all of the lower bits.
184		* See PCI Spec 6.2.5.1 ...
	201	* See PCI Spec 6.2.5.1.
185	202	*/
186	203	limit = 0;
…	…
188	205	resource->size = 1;
189	206	resource->align = resource->gran = 0;
190		while(!(moving & resource->size)) {
	207	while (!(moving & resource->size)) {
191	208	resource->size <<= 1;
192	209	resource->align += 1;
193		resource->gran += 1;
	210	resource->gran += 1;
194	211	}
195	212	resource->limit = limit = moving \| (resource->size - 1);
196	213	}
197		/*
198		* some broken hardware has read-only registers that do not
	214
	215	/* Some broken hardware has read-only registers that do not
199	216	* really size correctly.
200		* Example: the ~~acer m~~7229 has BARs 1-4 normally read-only.
	217	* Example: the Acer M7229 has BARs 1-4 normally read-only.
201	218	* so BAR1 at offset 0x10 reads 0x1f1. If you size that register
202	219	* by writing 0xffffffff to it, it will read back as 0x1f1 -- a
…	…
208	225	if (moving == 0) {
209	226	if (value != 0) {
210		printk_debug(
211		"%s register %02lx(%08lx), read-only ignoring it\n",
212		dev_path(dev), index, value);
	227	printk_debug
	228	("%s register %02lx(%08lx), read-only ignoring it\n",
	229	dev_path(dev), index, value);
213	230	}
214	231	resource->flags = 0;
215		}
216		else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
217		/* An I/O mapped base address */
	232	} else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
	233	/* An I/O mapped base address. */
218	234	attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
219	235	resource->flags \|= IORESOURCE_IO;
220		/* I don't want to deal with 32bit I/O resources */
	236	/* I don't want to deal with 32bit I/O resources. */
221	237	resource->limit = 0xffff;
222		}
223		else {
224		/* A Memory mapped base address */
	238	} else {
	239	/* A Memory mapped base address. */
225	240	attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
226	241	resource->flags \|= IORESOURCE_MEM;
…	…
230	245	attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
231	246	if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
232		/* 32bit limit */
	247	/* 32bit limit. */
233	248	resource->limit = 0xffffffffUL;
234		}
235		else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
236		/* 1MB limit */
	249	} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
	250	/* 1MB limit. */
237	251	resource->limit = 0x000fffffUL;
238		}
239		else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
240		/* 64bit limit */
	252	} else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
	253	/* 64bit limit. */
241	254	resource->limit = 0xffffffffffffffffULL;
242	255	resource->flags \|= IORESOURCE_PCI64;
243		}
244		else {
245		/* Invalid value */
	256	} else {
	257	/* Invalid value. */
	258	printk_err("Broken BAR with value %lx\n", attr);
	259	printk_err(" on dev %s at index %02lx\n",
	260	dev_path(dev), index);
246	261	resource->flags = 0;
247	262	}
248	263	}
249		/* Don't let the limit exceed which bits can move */
	264	/* Don't let the limit exceed which bits can move. */
250	265	if (resource->limit > limit) {
251	266	resource->limit = limit;
252	267	}
253		~~#if 0~~
254		~~if (resource->flags) {~~
255		~~printk_debug("%s %02x ->",~~
256		~~dev_path(dev), resource->index);~~
257		~~printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",~~
258		~~value, zeroes, ones, attr);~~
259		~~printk_debug(~~
260		~~"%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ",~~
261		~~dev_path(dev),~~
262		~~resource->index,~~
263		~~resource->size, resource->limit,~~
264		~~resource_type(resource));~~
265		}
266		~~#endif~~
267	268
268	269	return resource;
269	270	}
270	271
	272	/**
	273	* Given a device and an index, read the size of the BAR for that register.
	274	*
	275	* @param dev Pointer to the device structure.
	276	* @param index Address of the PCI configuration register.
	277	*/
271	278	static void pci_get_rom_resource(struct device *dev, unsigned long index)
272	279	{
273	280	struct resource *resource;
274	281	unsigned long value;
275		resource_t moving;
276
277		if ((dev->on_mainboard) && (dev->rom_address == 0)) {
278		/~~/skip it if rom_address is not set in MB Config.lb~~
279		return;
280		}
281
282		/* Initialize the resources to nothing */
	282	resource_t moving;
	283
	284	if ((dev->on_mainboard) && (dev->rom_address == 0)) {
	285	/* Skip it if rom_address is not set in the MB Config.lb. */
	286	return;
	287	}
	288
	289	/* Initialize the resources to nothing. */
283	290	resource = new_resource(dev, index);
284	291
285		/* Get the initial value */
	292	/* Get the initial value. */
286	293	value = pci_read_config32(dev, index);
287	294
288		/* See which bits move */
	295	/* See which bits move. */
289	296	moving = pci_moving_config32(dev, index);
290		/* clear the Enable bit */
	297
	298	/* Clear the Enable bit. */
291	299	moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
292	300
293	301	/* Find the resource constraints.
294		*
295	302	* Start by finding the bits that move. From there:
296	303	* - Size is the least significant bit of the bits that move.
297	304	* - Limit is all of the bits that move plus all of the lower bits.
298		* See PCI Spec 6.2.5.1 ...
	305	* See PCI Spec 6.2.5.1.
299	306	*/
300	307	if (moving) {
…	…
304	311	resource->size <<= 1;
305	312	resource->align += 1;
306		resource->gran += 1;
	313	resource->gran += 1;
307	314	}
308	315	resource->limit = moving \| (resource->size - 1);
309		}
310
311		if (moving == 0) {
	316	resource->flags \|= IORESOURCE_MEM \| IORESOURCE_READONLY;
	317	} else {
312	318	if (value != 0) {
313		printk_debug("%s register %02lx(%08lx), read-only ignoring it\n",
314		dev_path(dev), index, value);
	319	printk_debug
	320	("%s register %02lx(%08lx), read-only ignoring it\n",
	321	dev_path(dev), index, value);
315	322	}
316	323	resource->flags = 0;
317		} else {
318		resource->flags \|= IORESOURCE_MEM \| IORESOURCE_READONLY;
319		}
320
321		/* for on board device with embedded ROM image, the ROM image is at
	324	}
	325
	326	/* For on board device with embedded ROM image, the ROM image is at
322	327	* fixed address specified in the Config.lb, the dev->rom_address is
323	328	* inited by driver_pci_onboard_ops::enable_dev() */
324	329	if ((dev->on_mainboard) && (dev->rom_address != 0)) {
325		resource->base = dev->rom_address;
	330	resource->base = dev->rom_address;
326	331	resource->flags \|= IORESOURCE_MEM \| IORESOURCE_READONLY \|
327		IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	332	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
328	333	}
329	334
…	…
331	336	}
332	337
333		/** Read the base address registers for a given device.
334		* @param dev Pointer to the dev structure
335		* @param howmany How many registers to read (6 for device, 2 for bridge)
	338	/**
	339	* Read the base address registers for a given device.
	340	*
	341	* @param dev Pointer to the dev structure.
	342	* @param howmany How many registers to read (6 for device, 2 for bridge).
336	343	*/
337	344	static void pci_read_bases(struct device *dev, unsigned int howmany)
…	…
339	346	unsigned long index;
340	347
341		for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
	348	for (index = PCI_BASE_ADDRESS_0;
	349	(index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
342	350	struct resource *resource;
343	351	resource = pci_get_resource(dev, index);
344		index += (resource->flags & IORESOURCE_PCI64)~~?8:~~4;
	352	index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
345	353	}
346	354
…	…
348	356	}
349	357
350		static void pci_set_resource(struct device dev, struct resource resource);
351
352		static void pci_record_bridge_resource(
353		struct device *dev, resource_t moving,
354		unsigned index, unsigned long mask, unsigned long type)
355		{
356		/* Initiliaze the constraints on the current bus */
	358	static void pci_record_bridge_resource(struct device *dev, resource_t moving,
	359	unsigned index, unsigned long type)
	360	{
	361	/* Initialize the constraints on the current bus. */
357	362	struct resource *resource;
358		resource = 0;
	363	resource = NULL;
359	364	if (moving) {
360	365	unsigned long gran;
…	…
364	369	gran = 0;
365	370	step = 1;
366		while((moving & step) == 0) {
	371	while ((moving & step) == 0) {
367	372	gran += 1;
368	373	step <<= 1;
…	…
371	376	resource->align = gran;
372	377	resource->limit = moving \| (step - 1);
373		resource->flags = type \| IORESOURCE_PCI_BRIDGE;
374		compute_allocate_resource(&dev->link[0], resource, mask, type);
375		/* If there is nothing behind the resource,
376		* clear it and forget it.
377		*/
378		if (resource->size == 0) {
379		#if CONFIG_PCI_64BIT_PREF_MEM == 1
380		resource->base = moving;
381		#else
382		resource->base = moving & 0xffffffff;
383		#endif
384		resource->flags \|= IORESOURCE_ASSIGNED;
385		resource->flags &= ~IORESOURCE_STORED;
386		pci_set_resource(dev, resource);
387		resource->flags = 0;
388		}
	378	resource->flags = type \| IORESOURCE_PCI_BRIDGE \|
	379	IORESOURCE_BRIDGE;
389	380	}
390	381	return;
…	…
395	386	resource_t moving_base, moving_limit, moving;
396	387
397		/* See if the bridge I/O resources are implemented */
398		moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
399		moving_base \|= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
400
401		moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
402		moving_limit \|= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
	388	/* See if the bridge I/O resources are implemented. */
	389	moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
	390	moving_base \|=
	391	((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
	392
	393	moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
	394	moving_limit \|=
	395	((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
403	396
404	397	moving = moving_base & moving_limit;
405	398
406		/* Initialize the io space constraints on the current bus */
407		pci_record_bridge_resource(
408		dev, moving, PCI_IO_BASE,
409		IORESOURCE_IO, IORESOURCE_IO);
410
411
412		/* See if the bridge prefmem resources are implemented */
413		moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
414		moving_base \|= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
415
416		moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
417		moving_limit \|= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
	399	/* Initialize the I/O space constraints on the current bus. */
	400	pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
	401
	402	/* See if the bridge prefmem resources are implemented. */
	403	moving_base =
	404	((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
	405	moving_base \|=
	406	((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) <<
	407	32;
	408
	409	moving_limit =
	410	((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) <<
	411	16;
	412	moving_limit \|=
	413	((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) <<
	414	32;
418	415
419	416	moving = moving_base & moving_limit;
420		/* Initiliaze the prefetchable memory constraints on the current bus */
421		pci_record_bridge_resource(
422		dev, moving, PCI_PREF_MEMORY_BASE,
423		IORESOURCE_MEM \| IORESOURCE_PREFETCH,
424		IORESOURCE_MEM \| IORESOURCE_PREFETCH);
425
426
427		/* See if the bridge mem resources are implemented */
428		moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
429		moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
	417	/* Initialize the prefetchable memory constraints on the current bus. */
	418	pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
	419	IORESOURCE_MEM \| IORESOURCE_PREFETCH);
	420
	421	/* See if the bridge mem resources are implemented. */
	422	moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
	423	moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
430	424
431	425	moving = moving_base & moving_limit;
432	426
433		/* Initialize the memory resources on the current bus */
434		pci_record_bridge_resource(
435		dev, moving, PCI_MEMORY_BASE,
436		IORESOURCE_MEM \| IORESOURCE_PREFETCH,
437		IORESOURCE_MEM);
	427	/* Initialize the memory resources on the current bus. */
	428	pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
	429	IORESOURCE_MEM);
438	430
439	431	compact_resources(dev);
…	…
453	445	}
454	446
	447	void pci_domain_read_resources(struct device *dev)
	448	{
	449	struct resource *res;
	450
	451	/* Initialize the system-wide I/O space constraints. */
	452	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
	453	res->limit = 0xffffUL;
	454	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	455	IORESOURCE_ASSIGNED;
	456
	457	/* Initialize the system-wide memory resources constraints. */
	458	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
	459	res->limit = 0xffffffffULL;
	460	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	461	IORESOURCE_ASSIGNED;
	462	}
	463
455	464	static void pci_set_resource(struct device dev, struct resource resource)
456	465	{
457	466	resource_t base, end;
458	467
459		/* Make certain the resource has actually been ~~set~~ */
	468	/* Make certain the resource has actually been assigned a value. */
460	469	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
461		printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n",
462		dev_path(dev), resource->index,
463		resource_type(resource),
464		resource->size);
	470	printk_err("ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
	471	dev_path(dev), resource->index,
	472	resource_type(resource), resource->size);
465	473	return;
466	474	}
467	475
468		/* If I have already stored this resource don't worry about it */
	476	/* If I have already stored this resource don't worry about it. */
469	477	if (resource->flags & IORESOURCE_STORED) {
470	478	return;
471	479	}
472	480
473		/* If the resource~~s is substractive don't worry about it~~ */
	481	/* If the resource is subtractive don't worry about it. */
474	482	if (resource->flags & IORESOURCE_SUBTRACTIVE) {
475	483	return;
476	484	}
477	485
478		/* Only handle PCI memory and I~~O resources for now~~ */
479		if (!(resource->flags & (IORESOURCE_MEM \|IORESOURCE_IO)))
	486	/* Only handle PCI memory and I/O resources for now. */
	487	if (!(resource->flags & (IORESOURCE_MEM \| IORESOURCE_IO)))
480	488	return;
481	489
482		/* Enable the resources in the command register */
	490	/* Enable the resources in the command register. */
483	491	if (resource->size) {
484	492	if (resource->flags & IORESOURCE_MEM) {
…	…
492	500	}
493	501	}
494		/* Get the base address */
	502	/* Get the base address. */
495	503	base = resource->base;
496	504
497		/* Get the end */
	505	/* Get the end. */
498	506	end = resource_end(resource);
499	507
500		/* Now store the resource */
	508	/* Now store the resource. */
501	509	resource->flags \|= IORESOURCE_STORED;
	510
	511	/* PCI Bridges have no enable bit. They are disabled if the base of
	512	* the range is greater than the limit. If the size is zero, disable
	513	* by setting the base = limit and end = limit - 2^gran.
	514	*/
	515	if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
	516	base = resource->limit;
	517	end = resource->limit - (1 << resource->gran);
	518	resource->base = base;
	519	}
	520
502	521	if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
503	522	unsigned long base_lo, base_hi;
504		/*
505		* some chipsets allow us to set/clear the IO bit.
506		* (e.g. VIA 82c686a.) So set it to be safe)
	523	/* Some chipsets allow us to set/clear the I/O bit
	524	* (e.g. VIA 82c686a). So set it to be safe.
507	525	*/
508	526	base_lo = base & 0xffffffff;
…	…
515	533	pci_write_config32(dev, resource->index + 4, base_hi);
516	534	}
517		}
518		else if (resource->index == PCI_IO_BASE) {
519		/* set the IO ranges */
520		compute_allocate_resource(&dev->link[0], resource,
521		IORESOURCE_IO, IORESOURCE_IO);
522		pci_write_config8(dev, PCI_IO_BASE, base >> 8);
	535	} else if (resource->index == PCI_IO_BASE) {
	536	/* Set the I/O ranges. */
	537	pci_write_config8(dev, PCI_IO_BASE, base >> 8);
523	538	pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
524		pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
	539	pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
525	540	pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
526		}
527		else if (resource->index == PCI_MEMORY_BASE) {
528		/* set the memory range */
529		compute_allocate_resource(&dev->link[0], resource,
530		IORESOURCE_MEM \| IORESOURCE_PREFETCH,
531		IORESOURCE_MEM);
	541	} else if (resource->index == PCI_MEMORY_BASE) {
	542	/* Set the memory range. */
532	543	pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
533	544	pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
534		}
535		else if (resource->index == PCI_PREF_MEMORY_BASE) {
536		/* set the prefetchable memory range */
537		compute_allocate_resource(&dev->link[0], resource,
538		IORESOURCE_MEM \| IORESOURCE_PREFETCH,
539		IORESOURCE_MEM \| IORESOURCE_PREFETCH);
	545	} else if (resource->index == PCI_PREF_MEMORY_BASE) {
	546	/* Set the prefetchable memory range. */
540	547	pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
541	548	pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
542	549	pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
543	550	pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
544		}
545		else {
546		/* Don't let me think I stored the resource */
	551	} else {
	552	/* Don't let me think I stored the resource. */
547	553	resource->flags &= ~IORESOURCE_STORED;
548	554	printk_err("ERROR: invalid resource->index %lx\n",
549		resource->index);
	555	resource->index);
550	556	}
551	557	report_resource_stored(dev, resource, "");
…	…
557	563	struct resource resource, last;
558	564	unsigned link;
559		u~~int8_t~~ line;
	565	u8 line;
560	566
561	567	last = &dev->resource[dev->resources];
562	568
563		for(resource = &dev->resource[0]; resource < last; resource++) {
	569	for (resource = &dev->resource[0]; resource < last; resource++) {
564	570	pci_set_resource(dev, resource);
565	571	}
566		for(link = 0; link < dev->links; link++) {
	572	for (link = 0; link < dev->links; link++) {
567	573	struct bus *bus;
568	574	bus = &dev->link[link];
…	…
572	578	}
573	579
574		/* ~~set a default latency timer~~ */
	580	/* Set a default latency timer. */
575	581	pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
576	582
577		/* ~~set a default secondary latency timer~~ */
	583	/* Set a default secondary latency timer. */
578	584	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
579	585	pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
580	586	}
581	587
582		/* ~~zero the irq settings~~ */
	588	/* Zero the IRQ settings. */
583	589	line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
584	590	if (line) {
585	591	pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
586	592	}
587		/* ~~set the cache line size, so far 64 bytes is good for everyone~~ */
	593	/* Set the cache line size, so far 64 bytes is good for everyone. */
588	594	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
589	595	}
…	…
592	598	{
593	599	const struct pci_operations *ops;
594		u~~int16_t~~ command;
595
596		/* Set the subsystem vendor and device id for mainboard devices */
	600	u16 command;
	601
	602	/* Set the subsystem vendor and device id for mainboard devices. */
597	603	ops = ops_pci(dev);
598	604	if (dev->on_mainboard && ops && ops->set_subsystem) {
599	605	printk_debug("%s subsystem <- %02x/%02x\n",
600		dev_path(dev),
601		CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
602		CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
	606	dev_path(dev),
	607	CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
	608	CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
603	609	ops->set_subsystem(dev,
604		CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
605		CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
	610	CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
	611	CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
606	612	}
607	613	command = pci_read_config16(dev, PCI_COMMAND);
608	614	command \|= dev->command;
	615	/* v3 has
	616	* command \|= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
	617	*/
609	618	printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
610	619	pci_write_config16(dev, PCI_COMMAND, command);
…	…
613	622	void pci_bus_enable_resources(struct device *dev)
614	623	{
615		uint16_t ctrl;
616		/* enable IO in command register if there is VGA card
617		* connected with (even it does not claim IO resource) */
	624	u16 ctrl;
	625
	626	/* Enable I/O in command register if there is VGA card
	627	* connected with (even it does not claim I/O resource).
	628	*/
618	629	if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
619	630	dev->command \|= PCI_COMMAND_IO;
620	631	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
621	632	ctrl \|= dev->link[0].bridge_ctrl;
622		ctrl \|= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); ~~/* error check~~ */
	633	ctrl \|= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
623	634	printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
624	635	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
625	636
626	637	pci_dev_enable_resources(dev);
627
628	638	enable_childrens_resources(dev);
629	639	}
…	…
641	651	}
642	652
643		void pci_dev_set_subsystem(~~device_t~~ dev, unsigned vendor, unsigned device)
	653	void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
644	654	{
645	655	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
646		((device & 0xffff) << 16) \| (vendor & 0xffff));
	656	((device & 0xffff) << 16) \| (vendor & 0xffff));
647	657	}
648	658
…	…
651	661	{
652	662	#if CONFIG_PCI_ROM_RUN == 1 \|\| CONFIG_VGA_ROM_RUN == 1
653		void run_bios(struct device * dev, unsigned long addr);
	663	void run_bios(struct device *dev, unsigned long addr);
654	664	struct rom_header rom, ram;
655	665
…	…
659	669	* all other option ROM types.
660	670	*/
661		if ((dev->class~~>>8)!=~~PCI_CLASS_DISPLAY_VGA)
	671	if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
662	672	return;
663	673	#endif
…	…
686	696
687	697	struct device_operations default_pci_ops_dev = {
688		.read_resources = pci_dev_read_resources,
689		.set_resources = pci_dev_set_resources,
	698	.read_resources = pci_dev_read_resources,
	699	.set_resources = pci_dev_set_resources,
690	700	.enable_resources = pci_dev_enable_resources,
691		.init = pci_dev_init,
692		.scan_bus = 0,
693		.enable = 0,
694		.ops_pci = &pci_dev_ops_pci,
	701	.init = pci_dev_init,
	702	.scan_bus = 0,
	703	.enable = 0,
	704	.ops_pci = &pci_dev_ops_pci,
695	705	};
696	706
…	…
701	711
702	712	struct device_operations default_pci_ops_bus = {
703		.read_resources = pci_bus_read_resources,
704		.set_resources = pci_dev_set_resources,
	713	.read_resources = pci_bus_read_resources,
	714	.set_resources = pci_dev_set_resources,
705	715	.enable_resources = pci_bus_enable_resources,
706		.init = 0,
707		.scan_bus = pci_scan_bridge,
708		.enable = 0,
709		.reset_bus = pci_bus_reset,
710		.ops_pci = &pci_bus_ops_pci,
	716	.init = 0,
	717	.scan_bus = pci_scan_bridge,
	718	.enable = 0,
	719	.reset_bus = pci_bus_reset,
	720	.ops_pci = &pci_bus_ops_pci,
711	721	};
712	722
…	…
714	724	* @brief Detect the type of downstream bridge
715	725	*
716		* This function is a heuristic to detect which type
717		* of bus is downstream of a pci to pci bridge. This
718		* functions by looking for various capability blocks
719		* to figure out the type of downstream bridge. PCI-X
720		* PCI-E, and Hypertransport all seem to have appropriate
721		* capabilities.
	726	* This function is a heuristic to detect which type of bus is downstream
	727	* of a PCI-to-PCI bridge. This functions by looking for various capability
	728	* blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
	729	* Hypertransport all seem to have appropriate capabilities.
722	730	*
723	731	* When only a PCI-Express capability is found the type
724	732	* is examined to see which type of bridge we have.
725	733	*
726		* @param dev
727		*
728		* @return appropriate bridge operations
	734	* @param dev Pointer to the device structure of the bridge.
	735	* @return Appropriate bridge operations.
729	736	*/
730	737	static struct device_operations *get_pci_bridge_ops(device_t dev)
…	…
744	751	#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
745	752	pos = 0;
746		while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
	753	while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
747	754	unsigned flags;
748	755	flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
…	…
750	757	/* Host or Secondary Interface */
751	758	printk_debug("%s subbordinate bus Hypertransport\n",
752		dev_path(dev));
	759	dev_path(dev));
753	760	return &default_ht_ops_bus;
754	761	}
…	…
760	767	unsigned flags;
761	768	flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
762		switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
	769	switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
763	770	case PCI_EXP_TYPE_ROOT_PORT:
764	771	case PCI_EXP_TYPE_UPSTREAM:
765	772	case PCI_EXP_TYPE_DOWNSTREAM:
766	773	printk_debug("%s subbordinate bus PCI Express\n",
767		dev_path(dev));
	774	dev_path(dev));
768	775	return &default_pciexp_ops_bus;
769	776	case PCI_EXP_TYPE_PCI_BRIDGE:
770		printk_debug("%s subbordinate PCI\n",
771		dev_path(dev));
	777	printk_debug("%s subbordinate PCI\n", dev_path(dev));
772	778	return &default_pci_ops_bus;
773	779	default:
…	…
780	786
781	787	/**
782		* @brief Set up PCI device operation
783		*
784		*
785		* @param dev
786		*
	788	* Set up PCI device operation. Check if it already has a driver. If not, use
	789	* find_device_operations, or set to a default based on type.
	790	*
	791	* @param dev Pointer to the device whose pci_ops you want to set.
787	792	* @see pci_drivers
788	793	*/
…	…
795	800
796	801	/* Look through the list of setup drivers and find one for
797		* this ~~pci device~~
798		*/
799		for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
	802	* this PCI device.
	803	*/
	804	for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
800	805	if ((driver->vendor == dev->vendor) &&
801		(driver->device == dev->device))
802		{
	806	(driver->device == dev->device)) {
803	807	dev->ops = driver->ops;
804	808	printk_spew("%s [%04x/%04x] %sops\n",
805		dev_path(dev),
806		driver->vendor, driver->device,
807		~~(driver->ops->scan_bus?"bus ":~~""));
	809	dev_path(dev),
	810	driver->vendor, driver->device,
	811	(driver->ops->scan_bus ? "bus " : ""));
808	812	return;
809	813	}
…	…
811	815
812	816	/* If I don't have a specific driver use the default operations */
813		switch(dev->hdr_type & 0x7f) { /* header type */
	817	switch (dev->hdr_type & 0x7f) { /* header type */
814	818	case PCI_HEADER_TYPE_NORMAL: /* standard header */
815	819	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
…	…
828	832	#endif
829	833	default:
830		bad:
	834	bad:
831	835	if (dev->enabled) {
832	836	printk_err("%s [%04x/%04x/%06x] has unknown header "
833		"type %02x, ignoring.\n",
834		dev_path(dev),
835		dev->vendor, dev->device,
836		dev->class >> 8, dev->hdr_type);
	837	"type %02x, ignoring.\n",
	838	dev_path(dev),
	839	dev->vendor, dev->device,
	840	dev->class >> 8, dev->hdr_type);
837	841	}
838	842	}
839	843	return;
840	844	}
841
842
843	845
844	846	/**
…	…
849	851	* removes the device structure from the linked list.
850	852	*
851		* @param list ~~the device structure list~~
852		* @param devfn ~~a device/function number~~
853		*
854		* @return ~~pointer to the device structure found or null o~~f we have not
	853	* @param list The device structure list.
	854	* @param devfn A device/function number.
	855	*
	856	* @return Pointer to the device structure found or NULL if we have not
855	857	* allocated a device for this devfn yet.
856	858	*/
…	…
859	861	struct device *dev;
860	862	dev = 0;
861		for(; list; list = &(list)->sibling) {
	863	for (; list; list = &(list)->sibling) {
862	864	if ((*list)->path.type != DEVICE_PATH_PCI) {
863	865	printk_err("child %s not a pci device\n",
864		dev_path(*list));
	866	dev_path(*list));
865	867	continue;
866	868	}
867	869	if ((*list)->path.pci.devfn == devfn) {
868		/* Unlink from the list */
	870	/* Unlink from the list. */
869	871	dev = *list;
870	872	list = (list)->sibling;
871		dev->sibling = 0;
	873	dev->sibling = NULL;
872	874	break;
873	875	}
874	876	}
875		/* Just like alloc_dev add the device to the list of device on the bus.
876		* When the list of devices was formed we removed all of the parents
877		* children, and now we are interleaving static and dynamic devices in
878		* order on the bus.
	877
	878	/* Just like alloc_dev() add the device to the list of devices on the
	879	* bus. When the list of devices was formed we removed all of the
	880	* parents children, and now we are interleaving static and dynamic
	881	* devices in order on the bus.
879	882	*/
880	883	if (dev) {
881		~~device_t~~ child;
882		/* Find the last child of our parent */
883		for~~(child = dev->bus->children; child && child->sibling;~~ ) {
	884	struct device *child;
	885	/* Find the last child of our parent. */
	886	for (child = dev->bus->children; child && child->sibling;) {
884	887	child = child->sibling;
885	888	}
886		/* Place the device on the list of children of it's parent. */
	889	/* Place the device on the list of children of its parent. */
887	890	if (child) {
888	891	child->sibling = dev;
…	…
898	901	* @brief Scan a PCI bus.
899	902	*
900		* Determine the existence of a given PCI device.
	903	* Determine the existence of a given PCI device. Allocate a new struct device
	904	* if dev==NULL was passed in and the device exists in hardware.
901	905	*
902	906	* @param bus pointer to the bus structure
…	…
906	910	* or the NULL if no device is found.
907	911	*/
908		device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
909		{
910		u~~int32_t~~ id, class;
911		u~~int8_t~~ hdr_type;
912
913		/* Detect if a device is present */
	912	device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
	913	{
	914	u32 id, class;
	915	u8 hdr_type;
	916
	917	/* Detect if a device is present. */
914	918	if (!dev) {
915	919	struct device dummy;
916		dummy.bus = bus;
917		dummy.path.type = DEVICE_PATH_PCI;
	920	dummy.bus = bus;
	921	dummy.path.type = DEVICE_PATH_PCI;
918	922	dummy.path.pci.devfn = devfn;
919	923	id = pci_read_config32(&dummy, PCI_VENDOR_ID);
920		/* Have we found somthing?
	924	/* Have we found something?
921	925	* Some broken boards return 0 if a slot is empty.
922	926	*/
923		if ( (id == 0xffffffff) \|\| (id == 0x00000000) \|\|
924		(id == 0x0000ffff) \|\| (id == 0xffff0000))
925		{
	927	if ((id == 0xffffffff) \|\| (id == 0x00000000) \|\|
	928	(id == 0x0000ffff) \|\| (id == 0xffff0000)) {
926	929	printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
927	930	return NULL;
928	931	}
929	932	dev = alloc_dev(bus, &dummy.path);
930		}
931		else {
932		/* Enable/disable the device. Once we have
933		* found the device specific operations this
934		* operations we will disable the device with
935		* those as well.
	933	} else {
	934	/* Enable/disable the device. Once we have found the device-
	935	* specific operations this operations we will disable the
	936	* device with those as well.
936	937	*
937	938	* This is geared toward devices that have subfunctions
…	…
939	940	*
940	941	* If a device is a stuff option on the motherboard
941		* it may be absent and enable_dev must cope.
942		*
	942	* it may be absent and enable_dev() must cope.
943	943	*/
944		/* Run the magic~~e enable sequence for the device~~ */
	944	/* Run the magic enable sequence for the device. */
945	945	if (dev->chip_ops && dev->chip_ops->enable_dev) {
946	946	dev->chip_ops->enable_dev(dev);
947	947	}
948		/* Now read the vendor and device id */
	948	/* Now read the vendor and device ID. */
949	949	id = pci_read_config32(dev, PCI_VENDOR_ID);
950	950
951
952		/* If the device does not have a pci id disable it.
953		* Possibly this is because we have already disabled
954		* the device. But this also handles optional devices
955		* that may not always show up.
	951	/* If the device does not have a PCI ID disable it. Possibly
	952	* this is because we have already disabled the device. But
	953	* this also handles optional devices that may not always
	954	* show up.
956	955	*/
957	956	/* If the chain is fully enumerated quit */
958		if ( (id == 0xffffffff) \|\| (id == 0x00000000) \|\|
959		(id == 0x0000ffff) \|\| (id == 0xffff0000))
960		{
	957	if ((id == 0xffffffff) \|\| (id == 0x00000000) \|\|
	958	(id == 0x0000ffff) \|\| (id == 0xffff0000)) {
961	959	if (dev->enabled) {
962	960	printk_info("Disabling static device: %s\n",
963		dev_path(dev));
	961	dev_path(dev));
964	962	dev->enabled = 0;
965	963	}
…	…
967	965	}
968	966	}
969		/* Read the rest of the ~~pci configuration information~~ */
	967	/* Read the rest of the PCI configuration information. */
970	968	hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
971	969	class = pci_read_config32(dev, PCI_CLASS_REVISION);
972	970
973		/* Store the interesting information in the device structure */
	971	/* Store the interesting information in the device structure. */
974	972	dev->vendor = id & 0xffff;
975	973	dev->device = (id >> 16) & 0xffff;
976	974	dev->hdr_type = hdr_type;
977		/* class code, the upper 3 bytes of PCI_CLASS_REVISION */
	975
	976	/* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
978	977	dev->class = class >> 8;
979	978
980
981		/* Architectural/System devices always need to
982		* be bus masters.
983		*/
	979	/* Architectural/System devices always need to be bus masters. */
984	980	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
985	981	dev->command \|= PCI_COMMAND_MASTER;
986	982	}
987		/* Look at the vendor and device id, or at least the
988		* header type and class and figure out which set of
989		* configuration methods to use. Unless we already
990		* have some pci ops.
	983	/* Look at the vendor and device ID, or at least the header type and
	984	* class and figure out which set of configuration methods to use.
	985	* Unless we already have some PCI ops.
991	986	*/
992	987	set_pci_ops(dev);
993	988
994		/* Now run the magic enable/disable sequence for the device */
	989	/* Now run the magic enable/disable sequence for the device. */
995	990	if (dev->ops && dev->ops->enable) {
996	991	dev->ops->enable(dev);
997	992	}
998	993
999
1000		/* Display the device and error if we don't have some pci operations
1001		* for it.
1002		*/
	994	/* Display the device. */
1003	995	printk_debug("%s [%04x/%04x] %s%s\n",
1004		dev_path(dev),
1005		dev->vendor, dev->device,
1006		dev->enabled?"enabled": "disabled",
1007		dev->ops?"" : " No operations"
1008		);
	996	dev_path(dev),
	997	dev->vendor, dev->device,
	998	dev->enabled ? "enabled" : "disabled",
	999	dev->ops ? "" : " No operations");
1009	1000
1010	1001	return dev;
…	…
1028	1019	*/
1029	1020	unsigned int pci_scan_bus(struct bus *bus,
1030		unsigned min_devfn, unsigned max_devfn,
1031		unsigned int max)
	1021	unsigned min_devfn, unsigned max_devfn,
	1022	unsigned int max)
1032	1023	{
1033	1024	unsigned int devfn;
1034		~~device_t~~ old_devices;
1035		~~device_t~~ child;
	1025	struct device *old_devices;
	1026	struct device *child;
1036	1027
1037	1028	#if CONFIG_PCI_BUS_SEGN_BITS
1038		printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
	1029	printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
	1030	bus->secondary >> 8, bus->secondary & 0xff);
1039	1031	#else
1040	1032	printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
…	…
1042	1034
1043	1035	old_devices = bus->children;
1044		bus->children = 0;
	1036	bus->children = NULL;
1045	1037
1046	1038	post_code(0x24);
1047		/* probe all devices/functions on this bus with some optimization for
1048		* non-existence and single func~~ion devices~~
	1039	/* Probe all devices/functions on this bus with some optimization for
	1040	* non-existence and single function devices.
1049	1041	*/
1050	1042	for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1051		~~device_t~~ dev;
	1043	struct device *dev;
1052	1044
1053	1045	/* First thing setup the device structure */
1054	1046	dev = pci_scan_get_dev(&old_devices, devfn);
1055	1047
1056		/* See if a device is present and setup the device
1057		* structure.
1058		*/
	1048	/* See if a device is present and setup the device structure. */
1059	1049	dev = pci_probe_dev(dev, bus, devfn);
1060	1050
1061		/* if this is not a multi function device,
1062		* or the device is not present don't waste
1063		* time probing another function.
	1051	/* If this is not a multi function device, or the device is
	1052	* not present don't waste time probing another function.
1064	1053	* Skip to next device.
1065	1054	*/
1066	1055	if ((PCI_FUNC(devfn) == 0x00) &&
1067		~~(!dev \|\| (dev->enabled && ((dev->hdr_type & 0x80) != 0x80))))~~
1068		{
	1056	(!dev
	1057	\|\| (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1069	1058	devfn += 0x07;
1070	1059	}
…	…
1072	1061	post_code(0x25);
1073	1062
1074		/* ~~Die if any left~~ over static devices are are found.
	1063	/* Warn if any leftover static devices are are found.
1075	1064	* There's probably a problem in the Config.lb.
1076		*/
1077		if(old_devices) {
	1065	*/
	1066	if (old_devices) {
1078	1067	device_t left;
1079		for(left = old_devices; left; left = left->sibling) {
1080		printk_err("%s\n", dev_path(left));
1081		}
1082		printk_warning("PCI: Left over static devices. Check your mainboard Config.lb\n");
1083		}
1084
1085		/* For all children that implement scan_bus (i.e. bridges)
	1068	printk_warning("PCI: Left over static devices:\n");
	1069	for (left = old_devices; left; left = left->sibling) {
	1070	printk_warning("%s\n", dev_path(left));
	1071	}
	1072	printk_warning("PCI: Check your mainboard Config.lb.\n");
	1073	}
	1074
	1075	/* For all children that implement scan_bus() (i.e. bridges)
1086	1076	* scan the bus behind that child.
1087	1077	*/
1088		for(child = bus->children; child; child = child->sibling) {
	1078	for (child = bus->children; child; child = child->sibling) {
1089	1079	max = scan_bus(child, max);
1090	1080	}
1091	1081
1092		/*
1093		* We've scanned the bus and so we know all about what's on
1094		* the other side of any bridges that may be on this bus plus
1095		* any devices.
1096		*
	1082	/* We've scanned the bus and so we know all about what's on the other
	1083	* side of any bridges that may be on this bus plus any devices.
1097	1084	* Return how far we've got finding sub-buses.
1098	1085	*/
…	…
1102	1089	}
1103	1090
1104
1105	1091	/**
1106	1092	* @brief Scan a PCI bridge and the buses behind the bridge.
…	…
1111	1097	* This function is the default scan_bus() method for PCI bridge devices.
1112	1098	*
1113		* @param dev pointer to the bridge device
1114		* @param max the highest bus number assgined up to now
1115		*
1116		* @return The maximum bus number found, after scanning all subordinate busses
	1099	* @param dev Pointer to the bridge device.
	1100	* @param max The highest bus number assigned up to now.
	1101	* @return The maximum bus number found, after scanning all subordinate buses.
1117	1102	*/
1118	1103	unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1119		unsigned int (do_scan_bus)(struct bus bus,
1120		unsigned min_devfn, unsigned max_devfn, unsigned int max))
	1104	unsigned int (do_scan_bus) (struct bus bus,
	1105	unsigned min_devfn,
	1106	unsigned max_devfn,
	1107	unsigned int max))
1121	1108	{
1122	1109	struct bus *bus;
1123		u~~int32_t~~ buses;
1124		u~~int16_t~~ cr;
	1110	u32 buses;
	1111	u16 cr;
1125	1112
1126	1113	printk_spew("%s for %s\n", __func__, dev_path(dev));
…	…
1142	1129	pci_write_config16(dev, PCI_STATUS, 0xffff);
1143	1130
1144		/*
1145		* Read the existing primary/secondary/subordinate bus
	1131	/* Read the existing primary/secondary/subordinate bus
1146	1132	* number configuration.
1147	1133	*/
…	…
1153	1139	*/
1154	1140	buses &= 0xff000000;
1155		buses \|= (((unsigned int) (dev->bus->secondary) << 0) \|
1156		~~((unsigned int)~~ (bus->secondary) << 8) \|
1157		~~((unsigned int)~~ (bus->subordinate) << 16));
	1141	buses \|= (((unsigned int)(dev->bus->secondary) << 0) \|
	1142	((unsigned int)(bus->secondary) << 8) \|
	1143	((unsigned int)(bus->subordinate) << 16));
1158	1144	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1159	1145
…	…
1167	1153	*/
1168	1154	bus->subordinate = max;
1169		buses = (buses & 0xff00ffff) \|
1170		((unsigned int) (bus->subordinate) << 16);
	1155	buses = (buses & 0xff00ffff) \| ((unsigned int)(bus->subordinate) << 16);
1171	1156	pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1172	1157	pci_write_config16(dev, PCI_COMMAND, cr);
…	…
1184	1169	* This function is the default scan_bus() method for PCI bridge devices.
1185	1170	*
1186		* @param dev pointer to the bridge device
	1171	* @param dev Pointer to the bridge device.
	1172	* @param max The highest bus number assigned up to now.
	1173	* @return The maximum bus number found, after scanning all subordinate buses.
	1174	*/
	1175	unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
	1176	{
	1177	return do_pci_scan_bridge(dev, max, pci_scan_bus);
	1178	}
	1179
	1180	/**
	1181	* @brief Scan a PCI domain.
	1182	*
	1183	* This function is the default scan_bus() method for PCI domains.
	1184	*
	1185	* @param dev pointer to the domain
1187	1186	* @param max the highest bus number assgined up to now
1188	1187	*
1189	1188	* @return The maximum bus number found, after scanning all subordinate busses
1190	1189	*/
1191		unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1192		{
1193		return do_pci_scan_bridge(dev, max, pci_scan_bus);
1194		}
1195
1196		/*
1197		Tell the EISA int controller this int must be level triggered
1198		THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
1199		*/
	1190	unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
	1191	{
	1192	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
	1193	return max;
	1194	}
	1195
	1196	/**
	1197	* Tell the EISA int controller this int must be level triggered.
	1198	*
	1199	* THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
	1200	*/
1200	1201	void pci_level_irq(unsigned char intNum)
1201	1202	{
1202		unsigned short intBits = inb(0x4d0) \| (((unsigned) inb(0x4d1)) << 8);
	1203	unsigned short intBits = inb(0x4d0) \| (((unsigned)inb(0x4d1)) << 8);
1203	1204
1204	1205	printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
…	…
1207	1208	printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
1208	1209
1209		// Write new values
1210		outb((unsigned char) intBits, 0x4d0);
1211		outb((unsigned char) (intBits >> 8), 0x4d1);
1212
1213		/* this seems like an error but is not ... */
1214		#if 1
	1210	/* Write new values. */
	1211	outb((unsigned char)intBits, 0x4d0);
	1212	outb((unsigned char)(intBits >> 8), 0x4d1);
	1213
	1214	/* This seems like an error but is not. */
1215	1215	if (inb(0x4d0) != (intBits & 0xff)) {
1216		printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1217		__func__, intBits &0xff, inb(0x4d0));
	1216	printk_err(
	1217	"%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
	1218	__func__, intBits & 0xff, inb(0x4d0));
1218	1219	}
1219	1220	if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
1220		printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1221		__func__, (intBits>>8) &0xff, inb(0x4d1));
1222		}
1223		#endif
1224		}
1225
1226		/*
1227		This function assigns IRQs for all functions contained within
1228		the indicated device address. If the device does not exist or does
1229		not require interrupts then this function has no effect.
1230
1231		This function should be called for each PCI slot in your system.
1232
1233		pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1234		this slot.
1235		The particular irq #s that are passed in depend on the routing inside
1236		your southbridge and on your motherboard.
1237
1238		-kevinh@ispiri.com
	1221	printk_err(
	1222	"%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
	1223	__func__, (intBits >> 8) & 0xff, inb(0x4d1));
	1224	}
	1225	}
	1226
	1227	/**
	1228	* This function assigns IRQs for all functions contained within the
	1229	* indicated device address. If the device does not exist or does not
	1230	* require interrupts then this function has no effect.
	1231	*
	1232	* This function should be called for each PCI slot in your system.
	1233	*
	1234	* pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
	1235	* this slot.
	1236	*
	1237	* The particular irq #s that are passed in depend on the routing inside
	1238	* your southbridge and on your motherboard.
	1239	*
	1240	* -kevinh@ispiri.com
	1241	*
1239	1242	*/
1240	1243	void pci_assign_irqs(unsigned bus, unsigned slot,
1241		const unsigned char pIntAtoD[4])
	1244	const unsigned char pIntAtoD[4])
1242	1245	{
1243	1246	unsigned functNum;
1244		~~device_t~~ pdev;
	1247	struct device *pdev;
1245	1248	unsigned char line;
1246	1249	unsigned char irq;
1247	1250	unsigned char readback;
1248	1251
1249		/* Each slot may contain up to eight functions */
	1252	/* Each slot may contain up to eight functions. */
1250	1253	for (functNum = 0; functNum < 8; functNum++) {
1251	1254	pdev = dev_find_slot(bus, (slot << 3) + functNum);
1252	1255
1253	1256	if (pdev) {
1254		line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1255
1256		/~~/ PCI spec says all other values are reserved~~
	1257	line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
	1258
	1259	/* PCI spec says all other values are reserved. */
1257	1260	if ((line >= 1) && (line <= 4)) {
1258	1261	irq = pIntAtoD[line - 1];
1259	1262
1260		printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1261		irq, bus, slot, functNum);
1262
1263		pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1264		pIntAtoD[line - 1]);
1265
1266		readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
	1263	printk_debug("Assigning IRQ %d to %d:%x.%d\n",
	1264	irq, bus, slot, functNum);
	1265
	1266	pci_write_config8(pdev, PCI_INTERRUPT_LINE,
	1267	pIntAtoD[line - 1]);
	1268
	1269	readback =
	1270	pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1267	1271	printk_debug(" Readback = %d\n", readback);
1268	1272
1269		// Change to level triggered
	1273	// Change to level triggered.
1270	1274	pci_level_irq(pIntAtoD[line - 1]);
1271	1275	}

trunk/coreboot-v2/src/devices/root_device.c

r3052	r4394
35	35	void root_dev_read_resources(device_t root)
36	36	{
37		struct resource *resource;
38
39		/* Initialize the system wide io space constraints */
40		resource = new_resource(root, 0);
41		resource->base = 0x400;
42		resource->size = 0;
43		resource->align = 0;
44		resource->gran = 0;
45		resource->limit = 0xffffUL;
46		resource->flags = IORESOURCE_IO;
47		compute_allocate_resource(&root->link[0], resource,
48		IORESOURCE_IO, IORESOURCE_IO);
49
50		/* Initialize the system wide memory resources constraints */
51		resource = new_resource(root, 1);
52		resource->base = 0;
53		resource->size = 0;
54		resource->align = 0;
55		resource->gran = 0;
56		resource->limit = 0xffffffffUL;
57		resource->flags = IORESOURCE_MEM;
58		compute_allocate_resource(&root->link[0], resource,
59		IORESOURCE_MEM, IORESOURCE_MEM);
	37	printk_err("%s should never be called.\n", __func__);
60	38	}
61	39
…	…
69	47	void root_dev_set_resources(device_t root)
70	48	{
71		struct bus *bus;
72
73		bus = &root->link[0];
74		compute_allocate_resource(bus,
75		&root->resource[0], IORESOURCE_IO, IORESOURCE_IO);
76		compute_allocate_resource(bus,
77		&root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
78		assign_resources(bus);
	49	printk_err("%s should never be called.\n", __func__);
79	50	}
80	51

trunk/coreboot-v2/src/include/device/device.h

r4271	r4394
70	70	unsigned int enabled : 1; /* set if we should enable the device */
71	71	unsigned int initialized : 1; /* set if we have initialized the device */
72		~~unsigned int have_resources : 1; /* Set if we have read the devices resources */~~
73	72	unsigned int on_mainboard : 1;
74	73	unsigned long rom_address;
75	74
76		u~~int8_t~~ command;
	75	u8 command;
77	76
78	77	/* Base registers for this device. I/O, MEM and Expansion ROM */
…	…
80	79	unsigned int resources;
81	80
82		/* link ~~are (down~~ stream) buses attached to the device, usually a leaf
	81	/* links are (downstream) buses attached to the device, usually a leaf
83	82	* device with no children have 0 buses attached and a bridge has 1 bus
84	83	*/
…	…
107	106	int reset_bus(struct bus *bus);
108	107	unsigned int scan_bus(struct device *bus, unsigned int max);
109		~~void compute_allocate_resource(struct bus bus, struct resource bridge,~~
110		~~unsigned long type_mask, unsigned long type);~~
111	108	void assign_resources(struct bus *bus);
112	109	void enable_resources(struct device *dev);
…	…
143	140
144	141	extern struct device_operations default_dev_ops_root;
	142	void pci_domain_read_resources(struct device *dev);
	143	unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
145	144	void root_dev_read_resources(device_t dev);
146	145	void root_dev_set_resources(device_t dev);

trunk/coreboot-v2/src/include/device/resource.h

r1982	r4394
1		#ifndef RESOURCE_H
2		#define RESOURCE_H
	1	#ifndef DEVICE_RESOURCE_H
	2	#define DEVICE_RESOURCE_H
3	3
4	4	#include <stdint.h>
…	…
20	20	* to the bus below.
21	21	*/
	22	#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */
22	23	#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */
23	24	#define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */
…	…
63	64
64	65
65		typedef u~~int64_t~~ resource_t;
	66	typedef u64 resource_t;
66	67	struct resource {
67	68	resource_t base; /* Base address of the resource */
…	…
75	76	};
76	77
77		/* Macros to generate index values for ~~subtractive~~ resources */
	78	/* Macros to generate index values for resources */
78	79	#define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) + LINK)
79	80	#define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff)
	81
	82	#define IOINDEX(IDX,LINK) (((LINK) << 16) + IDX)
	83	#define IOINDEX_LINK(IDX) (( IDX & 0xf0000) >> 16)
	84	#define IOINDEX_IDX(IDX) (IDX & 0xffff)
80	85
81	86	/* Generic resource helper functions */
…	…
102	107	extern const char resource_type(struct resource resource);
103	108
104		#endif /* RESOURCE_H */
	109	#endif /* DEVICE_RESOURCE_H */

trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c

r4381	r4394
342	342	continue;
343	343	for(link = 0; !res && (link < 8); link++) {
344		res = probe_resource(dev, ~~0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1,~~
	344	res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
345	345	}
346	346	}
…	…
386	386	}
387	387
388		~~resource = new_resource(dev, 0x1000 + reg + (link<<16~~));
	388	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
389	389
390	390	return resource;
…	…
422	422
423	423	}
424		resource = new_resource(dev, ~~0x1000 + reg + (link<<16~~));
	424	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
425	425	return resource;
426	426	}
…	…
448	448	resource->limit = 0xffffUL;
449	449	resource->flags = IORESOURCE_IO;
450		~~compute_allocate_resource(&dev->link[link], resource,~~
451		~~IORESOURCE_IO, IORESOURCE_IO);~~
452	450	}
453	451
…	…
461	459	resource->limit = 0xffffffffffULL;
462	460	resource->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH;
463		~~compute_allocate_resource(&dev->link[link], resource,~~
464		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
465		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH);~~
466	461
467	462	#if CONFIG_EXT_CONF_SUPPORT == 1
…	…
482	477	resource->limit = 0xffffffffffULL;
483	478	resource->flags = IORESOURCE_MEM;
484		~~compute_allocate_resource(&dev->link[link], resource,~~
485		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
486		~~IORESOURCE_MEM);~~
487	479
488	480	#if CONFIG_EXT_CONF_SUPPORT == 1
…	…
542	534	/* Get the register and link */
543	535	reg = resource->index & 0xfff; // 4k
544		link = ~~( resource->index>> 16)& 0x7; // 8 links~~
	536	link = IOINDEX_LINK(resource->index);
545	537
546	538	if (resource->flags & IORESOURCE_IO) {
547		~~compute_allocate_resource(&dev->link[link], resource,~~
548		~~IORESOURCE_IO, IORESOURCE_IO);~~
549	539
550	540	set_io_addr_reg(dev, nodeid, link, reg, rbase>>8, rend>>8);
…	…
552	542	}
553	543	else if (resource->flags & IORESOURCE_MEM) {
554		~~compute_allocate_resource(&dev->link[link], resource,~~
555		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
556		~~resource->flags & (IORESOURCE_MEM \| IORESOURCE_PREFETCH));~~
557	544	set_mmio_addr_reg(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
558	545	store_conf_mmio_addr(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8);
…	…
658	645	};
659	646
660		static void ~~pci~~_domain_read_resources(device_t dev)
	647	static void amdfam10_domain_read_resources(device_t dev)
661	648	{
662	649	struct resource *resource;
…	…
673	660	if ((base & 3) != 0) {
674	661	unsigned nodeid, link;
675		device_t dev;
	662	device_t reg_dev;
676	663	if(reg<0xc0) { // mmio
677	664	nodeid = (limit & 0xf) + (base&0x30);
…	…
680	667	}
681	668	link = (limit >> 4) & 7;
682		dev = __f0_dev[nodeid];
683		if (dev) {
684		/* Reserve the resource */
685		struct resource *resource;
686		re~~source = new_resource(dev, 0x1000 + reg + (link<<16~~));
687		if (resource) {
688		resource->flags = 1;
	669	reg_dev = __f0_dev[nodeid];
	670	if (reg_dev) {
	671	/* Reserve the resource */
	672	struct resource *reg_resource;
	673	reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, link));
	674	if (reg_resource) {
	675	reg_resource->flags = 1;
689	676	}
690	677	}
…	…
712	699	resource->limit = 0xffffUL;
713	700	resource->flags = IORESOURCE_IO;
714		~~compute_allocate_resource(&dev->link[link], resource,~~
715		~~IORESOURCE_IO, IORESOURCE_IO);~~
716	701
717	702	/* Initialize the system wide prefetchable memory resources constraints */
…	…
719	704	resource->limit = 0xfcffffffffULL;
720	705	resource->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH;
721		~~compute_allocate_resource(&dev->link[link], resource,~~
722		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
723		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH);~~
724	706
725	707	/* Initialize the system wide memory resources constraints */
…	…
727	709	resource->limit = 0xfcffffffffULL;
728	710	resource->flags = IORESOURCE_MEM;
729		~~compute_allocate_resource(&dev->link[link], resource,~~
730		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
731		~~IORESOURCE_MEM);~~
732	711	}
733	712	#endif
…	…
770	749	return tolm;
771	750	}
772
773		~~#if CONFIG_PCI_64BIT_PREF_MEM == 1~~
774		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM \| IORESOURCE_PREFETCH)~~
775		~~#endif~~
776	751
777	752	#if CONFIG_HW_MEM_HOLE_SIZEK != 0
…	…
981	956	resource->flags &= ~IORESOURCE_STORED;
982	957	link = (resource>>2) & 3;
983		~~compute_allocate_resource(&dev->link[link], resource,~~
984		~~BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);~~
985
986	958	resource->flags \|= IORESOURCE_STORED;
987	959	report_resource_stored(dev, resource, "");
…	…
1143	1115	}
1144	1116
1145		static u32 ~~pci~~_domain_scan_bus(device_t dev, u32 max)
	1117	static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
1146	1118	{
1147	1119	u32 reg;
…	…
1193	1165
1194	1166	static struct device_operations pci_domain_ops = {
1195		.read_resources = ~~pci~~_domain_read_resources,
	1167	.read_resources = amdfam10_domain_read_resources,
1196	1168	.set_resources = pci_domain_set_resources,
1197	1169	.enable_resources = enable_childrens_resources,
1198	1170	.init = 0,
1199		.scan_bus = ~~pci~~_domain_scan_bus,
	1171	.scan_bus = amdfam10_domain_scan_bus,
1200	1172	#if CONFIG_MMCONF_SUPPORT_DEFAULT
1201	1173	.ops_pci_bus = &pci_ops_mmconf,

trunk/coreboot-v2/src/northbridge/amd/amdk8/misc_control.c

r4381	r4394
54	54	/* Add a Gart apeture resource */
55	55	resource = new_resource(dev, 0x94);
56		resource->size = ~~iommu?CONFIG_AGP_APERTURE_SIZE:1~~;
	56	resource->size = CONFIG_AGP_APERTURE_SIZE;
57	57	resource->align = log2(resource->size);
58	58	resource->gran = log2(resource->size);

trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c

r4381	r4394
298	298	continue;
299	299	for(link = 0; !res && (link < 3); link++) {
300		res = probe_resource(dev, ~~0x100 + (reg \|~~ link));
	300	res = probe_resource(dev, IOINDEX(0x100 + reg, link));
301	301	}
302	302	}
…	…
336	336	}
337	337	if (reg > 0) {
338		resource = new_resource(dev, ~~0x100 + (reg \|~~ link));
	338	resource = new_resource(dev, IOINDEX(0x100 + reg, link));
339	339	}
340	340	return resource;
…	…
363	363	}
364	364	if (reg > 0) {
365		resource = new_resource(dev, ~~0x100 + (reg \|~~ link));
	365	resource = new_resource(dev, IOINDEX(0x100 + reg, link));
366	366	}
367	367	return resource;
…	…
380	380	resource->gran = log2(HT_IO_HOST_ALIGN);
381	381	resource->limit = 0xffffUL;
382		resource->flags = IORESOURCE_IO;
383		compute_allocate_resource(&dev->link[link], resource,
384		IORESOURCE_IO, IORESOURCE_IO);
	382	resource->flags = IORESOURCE_IO \| IORESOURCE_BRIDGE;
385	383	}
386	384
…	…
394	392	resource->limit = 0xffffffffffULL;
395	393	resource->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH;
396		compute_allocate_resource(&dev->link[link], resource,
397		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
398		IORESOURCE_MEM \| IORESOURCE_PREFETCH);
	394	#ifdef CONFIG_PCI_64BIT_PREF_MEM
	395	resource->flags \|= IORESOURCE_BRIDGE;
	396	#endif
399	397	}
400	398
…	…
406	404	resource->align = log2(HT_MEM_HOST_ALIGN);
407	405	resource->gran = log2(HT_MEM_HOST_ALIGN);
408		resource->limit = 0xffffffffffULL;
409		resource->flags = IORESOURCE_MEM;
410		compute_allocate_resource(&dev->link[link], resource,
411		IORESOURCE_MEM \| IORESOURCE_PREFETCH,
412		IORESOURCE_MEM);
	406	resource->limit = 0xffffffffULL;
	407	resource->flags = IORESOURCE_MEM \| IORESOURCE_BRIDGE;
413	408	}
414	409	}
…	…
433	428	/* Make certain the resource has actually been set */
434	429	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
	430	printk_err("%s: can't set unassigned resource @%lx %lx\n",
	431	__func__, resource->index, resource->flags);
435	432	return;
436	433	}
…	…
438	435	/* If I have already stored this resource don't worry about it */
439	436	if (resource->flags & IORESOURCE_STORED) {
	437	printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
	438	resource->index, resource->flags);
440	439	return;
441	440	}
…	…
449	448	return;
450	449	}
	450
	451	if (resource->size == 0)
	452	return;
	453
451	454	/* Get the base address */
452	455	rbase = resource->base;
…	…
457	460	/* Get the register and link */
458	461	reg = resource->index & 0xfc;
459		link = ~~resource->index & 3~~;
	462	link = IOINDEX_LINK(resource->index);
460	463
461	464	if (resource->flags & IORESOURCE_IO) {
462	465	uint32_t base, limit;
463		~~compute_allocate_resource(&dev->link[link], resource,~~
464		~~IORESOURCE_IO, IORESOURCE_IO);~~
465	466	base = f1_read_config32(reg);
466	467	limit = f1_read_config32(reg + 0x4);
…	…
487	488	else if (resource->flags & IORESOURCE_MEM) {
488	489	uint32_t base, limit;
489		~~compute_allocate_resource(&dev->link[link], resource,~~
490		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
491		~~resource->flags & (IORESOURCE_MEM \| IORESOURCE_PREFETCH));~~
492	490	base = f1_read_config32(reg);
493	491	limit = f1_read_config32(reg + 0x4);
…	…
635	633	};
636	634
637		static void ~~pci~~_domain_read_resources(device_t dev)
	635	static void amdk8_domain_read_resources(device_t dev)
638	636	{
639	637	struct resource *resource;
…	…
656	654	/* Reserve the resource */
657	655	struct resource *reg_resource;
658		reg_resource = new_resource(reg_dev, ~~0x100 + (reg \|~~ link));
	656	reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
659	657	if (reg_resource) {
660	658	reg_resource->flags = 1;
…	…
663	661	}
664	662	}
665		#if CONFIG_PCI_64BIT_PREF_MEM == 0
666		/* Initialize the system wide io space constraints */
667		resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
668		resource->base = 0x400;
669		resource->limit = 0xffffUL;
670		resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
671
672		/* Initialize the system wide memory resources constraints */
673		resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
674		resource->limit = 0xfcffffffffULL;
675		resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
676		#else
677		/* Initialize the system wide io space constraints */
678		resource = new_resource(dev, 0);
679		resource->base = 0x400;
680		resource->limit = 0xffffUL;
681		resource->flags = IORESOURCE_IO;
682		compute_allocate_resource(&dev->link[0], resource,
683		IORESOURCE_IO, IORESOURCE_IO);
684
	663
	664	pci_domain_read_resources(dev);
	665
	666	#if CONFIG_PCI_64BIT_PREF_MEM == 1
685	667	/* Initialize the system wide prefetchable memory resources constraints */
686		resource = new_resource(dev, 1);
	668	resource = new_resource(dev, 2);
687	669	resource->limit = 0xfcffffffffULL;
688	670	resource->flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH;
689		~~compute_allocate_resource(&dev->link[0], resource,~~
690		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
691		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH);~~
692
693		~~/* Initialize the system wide memory resources constraints */~~
694		~~resource = new_resource(dev, 2);~~
695		~~resource->limit = 0xfcffffffffULL;~~
696		~~resource->flags = IORESOURCE_MEM;~~
697		~~compute_allocate_resource(&dev->link[0], resource,~~
698		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
699		~~IORESOURCE_MEM);~~
700	671	#endif
701	672	}
…	…
739	710	return tolm;
740	711	}
741
742		~~#if CONFIG_PCI_64BIT_PREF_MEM == 1~~
743		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM \| IORESOURCE_PREFETCH)~~
744		~~#endif~~
745	712
746	713	#if CONFIG_HW_MEM_HOLE_SIZEK != 0
…	…
899	866	#endif
900	867
901		static void ~~pci~~_domain_set_resources(device_t dev)
	868	static void amdk8_domain_set_resources(device_t dev)
902	869	{
903	870	#if CONFIG_PCI_64BIT_PREF_MEM == 1
…	…
965	932	for(resource = &dev->resource[0]; resource < last; resource++)
966	933	{
967		~~#if 1~~
968	934	resource->flags \|= IORESOURCE_ASSIGNED;
969		~~resource->flags &= ~IORESOURCE_STORED;~~
970		~~#endif~~
971		~~compute_allocate_resource(&dev->link[0], resource,~~
972		~~BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);~~
973
974	935	resource->flags \|= IORESOURCE_STORED;
975	936	report_resource_stored(dev, resource, "");
…	…
1126	1087	}
1127	1088
1128		static unsigned int ~~pci~~_domain_scan_bus(device_t dev, unsigned int max)
	1089	static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
1129	1090	{
1130	1091	unsigned reg;
…	…
1161	1122
1162	1123	static struct device_operations pci_domain_ops = {
1163		.read_resources = ~~pci~~_domain_read_resources,
1164		.set_resources = ~~pci~~_domain_set_resources,
	1124	.read_resources = amdk8_domain_read_resources,
	1125	.set_resources = amdk8_domain_set_resources,
1165	1126	.enable_resources = enable_childrens_resources,
1166	1127	.init = 0,
1167		.scan_bus = ~~pci~~_domain_scan_bus,
	1128	.scan_bus = amdk8_domain_scan_bus,
1168	1129	.ops_pci_bus = &pci_cf8_conf1,
1169	1130	};

trunk/coreboot-v2/src/northbridge/amd/gx1/northbridge.c

r4381	r4394
67	67	};
68	68
69
70
71		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
72
73		~~static void pci_domain_read_resources(device_t dev)~~
74		{
75		~~struct resource *resource;~~
76
77		~~printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);~~
78
79		~~/* Initialize the system wide io space constraints */~~
80		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
81		~~resource->limit = 0xffffUL;~~
82		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
83
84		~~/* Initialize the system wide memory resources constraints */~~
85		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
86		~~resource->limit = 0xffffffffULL;~~
87		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
88		}
89
90	69	static void ram_resource(device_t dev, unsigned long index,
91	70	unsigned long basek, unsigned long sizek)
…	…
186	165	}
187	166	assign_resources(&dev->link[0]);
188		}
189
190		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
191		{
192		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
193		~~return max;~~
194	167	}
195	168

trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c

r4381	r4394
357	357	};
358	358
359		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
360
361		~~static void pci_domain_read_resources(device_t dev)~~
362		{
363		~~struct resource *resource;~~
364
365		~~printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);~~
366
367		~~/* Initialize the system wide io space constraints */~~
368		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
369		~~resource->limit = 0xffffUL;~~
370		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
371
372		~~/* Initialize the system wide memory resources constraints */~~
373		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
374		~~resource->limit = 0xffffffffULL;~~
375		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
376		}
377
378	359	static void ram_resource(device_t dev, unsigned long index,
379	360	unsigned long basek, unsigned long sizek)
…	…
467	448	#endif
468	449	assign_resources(&dev->link[0]);
469		}
470
471		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
472		{
473		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
474		~~return max;~~
475	450	}
476	451

trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c

r4381	r4394
74	74	#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)\|(bizarro<<28)\|(ibase>>12), .lo=(ibase<<20)\|imask}}
75	75	#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)\|(bizarro<<28), .lo=(en<<24)\|(wen<<21)\|(ren<<20)\|(ibase<<3)}}
76
77		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
78	76
79	77	extern void graphics_init(void);
…	…
383	381	};
384	382
385		~~static void pci_domain_read_resources(device_t dev)~~
386		{
387		~~struct resource *resource;~~
388		~~printk_spew(">> Entering northbridge.c: %s\n", __func__);~~
389
390		~~/* Initialize the system wide io space constraints */~~
391		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
392		~~resource->limit = 0xffffUL;~~
393		~~resource->flags =~~
394		~~IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
395
396		~~/* Initialize the system wide memory resources constraints */~~
397		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
398		~~resource->limit = 0xffffffffULL;~~
399		~~resource->flags =~~
400		~~IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
401		}
402
403	383	static void ram_resource(device_t dev, unsigned long index,
404	384	unsigned long basek, unsigned long sizek)
…	…
471	451	}
472	452
473		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
474		{
475		~~printk_spew(">> Entering northbridge.c: %s\n", __func__);~~
476
477		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
478		~~return max;~~
479		}
480
481	453	static struct device_operations pci_domain_ops = {
482	454	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/ibm/cpc710/cpc710_northbridge.c

r2490	r4394
9	9	#include <cpu/cpu.h>
10	10	#include "chip.h"
11
12		~~static void pci_domain_read_resources(device_t dev)~~
13		{
14		~~struct resource *resource;~~
15
16		~~/* Initialize the system wide io space constraints */~~
17		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
18		~~resource->base = 0;~~
19		~~resource->limit = 0xffffUL;~~
20		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
21
22		~~/* Initialize the system wide memory resources constraints */~~
23		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
24		~~resource->base = 0x80000000ULL;~~
25		~~resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */~~
26		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
27		}
28	11
29	12	static void ram_resource(device_t dev, unsigned long index,
…	…
52	35	/* And assign the resources */
53	36	assign_resources(&dev->link[0]);
54		}
55
56
57		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
58		{
59		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
60		~~return max;~~
61	37	}
62	38

trunk/coreboot-v2/src/northbridge/ibm/cpc925/cpc925_northbridge.c

r2490	r4394
9	9	#include <cpu/cpu.h>
10	10	#include "chip.h"
11
12		~~static void pci_domain_read_resources(device_t dev)~~
13		{
14		~~struct resource *resource;~~
15
16		~~/* Initialize the system wide io space constraints */~~
17		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
18		~~resource->base = 0;~~
19		~~resource->limit = 0xffffUL;~~
20		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
21
22		~~/* Initialize the system wide memory resources constraints */~~
23		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
24		~~resource->base = 0x80000000ULL;~~
25		~~resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */~~
26		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
27		}
28	11
29	12	static void ram_resource(device_t dev, unsigned long index,
…	…
52	35	/* And assign the resources */
53	36	assign_resources(&dev->link[0]);
54		}
55
56
57		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
58		{
59		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
60		~~return max;~~
61	37	}
62	38

trunk/coreboot-v2/src/northbridge/intel/e7501/northbridge.c

r4381	r4394
9	9	#include <bitops.h>
10	10	#include "chip.h"
11
12		~~static void pci_domain_read_resources(device_t dev)~~
13		{
14		~~struct resource *resource;~~
15		~~unsigned reg;~~
16
17		~~/* Initialize the system wide io space constraints */~~
18		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
19		~~resource->base = 0x400; //yhlu~~
20		~~resource->limit = 0xffffUL;~~
21		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
22
23		~~/* Initialize the system wide memory resources constraints */~~
24		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
25		~~resource->limit = 0xffffffffULL;~~
26		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
27		}
28	11
29	12	static void ram_resource(device_t dev, unsigned long index,
…	…
156	139	}
157	140
158		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
159		{
160		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
161		~~return max;~~
162		}
163
164	141	static struct device_operations pci_domain_ops = {
165	142	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/intel/e7520/northbridge.c

r4381	r4394
29	29	}
30	30
31
32		~~static void pci_domain_read_resources(device_t dev)~~
33		{
34		~~struct resource *resource;~~
35
36		~~/* Initialize the system wide io space constraints */~~
37		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
38		~~resource->base = 0;~~
39		~~resource->size = 0;~~
40		~~resource->align = 0;~~
41		~~resource->gran = 0;~~
42		~~resource->limit = 0xffffUL;~~
43		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
44
45		~~/* Initialize the system wide memory resources constraints */~~
46		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
47		~~resource->base = 0;~~
48		~~resource->size = 0;~~
49		~~resource->align = 0;~~
50		~~resource->gran = 0;~~
51		~~resource->limit = 0xffffffffUL;~~
52		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
53		}
54
55	31	static void tolm_test(void gp, struct device dev, struct resource *new)
56	32	{
…	…
91	67	#if 1
92	68	printk_debug("PCI mem marker = %x\n", pci_tolm);
93		#endif
	69	#endif
94	70	/* FIXME Me temporary hack */
95	71	if(pci_tolm > 0xe0000000)
…	…
123	99	remaplimitk = 0 << 16;
124	100	remapoffsetk = 0 << 16;
125		}
	101	}
126	102	else {
127	103	/* The PCI memory hole overlaps memory
…	…
166	142	}
167	143	if (remaplimitk >= remapbasek) {
168		ram_resource(dev, 6, remapbasek,
	144	ram_resource(dev, 6, remapbasek,
169	145	(remaplimitk + 64*1024) - remapbasek);
170	146	}
…	…
179	155	}
180	156
181		static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
182		{
183		max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
184		if (max > max_bus) {
185		max_bus = max;
186		}
187		return max;
	157	static u32 e7520_domain_scan_bus(device_t dev, u32 max)
	158	{
	159	max_bus = pci_domain_scan_bus(dev, max);
	160	return max_bus;
188	161	}
189	162
…	…
193	166	.enable_resources = enable_childrens_resources,
194	167	.init = 0,
195		.scan_bus = ~~pci~~_domain_scan_bus,
	168	.scan_bus = e7520_domain_scan_bus,
196	169	.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
197	170	};

trunk/coreboot-v2/src/northbridge/intel/e7525/northbridge.c

r4381	r4394
29	29	}
30	30
31
32		~~static void pci_domain_read_resources(device_t dev)~~
33		{
34		~~struct resource *resource;~~
35
36		~~/* Initialize the system wide io space constraints */~~
37		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
38		~~resource->base = 0;~~
39		~~resource->size = 0;~~
40		~~resource->align = 0;~~
41		~~resource->gran = 0;~~
42		~~resource->limit = 0xffffUL;~~
43		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
44
45		~~/* Initialize the system wide memory resources constraints */~~
46		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
47		~~resource->base = 0;~~
48		~~resource->size = 0;~~
49		~~resource->align = 0;~~
50		~~resource->gran = 0;~~
51		~~resource->limit = 0xffffffffUL;~~
52		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
53		}
54
55	31	static void tolm_test(void gp, struct device dev, struct resource *new)
56	32	{
…	…
91	67	#if 1
92	68	printk_debug("PCI mem marker = %x\n", pci_tolm);
93		#endif
	69	#endif
94	70	/* FIXME Me temporary hack */
95	71	if(pci_tolm > 0xe0000000)
…	…
123	99	remaplimitk = 0 << 16;
124	100	remapoffsetk = 0 << 16;
125		}
	101	}
126	102	else {
127	103	/* The PCI memory hole overlaps memory
…	…
161	137	/* Report the memory regions */
162	138	ram_resource(dev, 3, 0, 640);
163		ram_resource(dev, 4, 768, ~~tolmk - 768~~);
	139	ram_resource(dev, 4, 768, (tolmk - 768));
164	140	if (tomk > 410241024) {
165	141	ram_resource(dev, 5, 40961024, tomk - 41024*1024);
166	142	}
167	143	if (remaplimitk >= remapbasek) {
168		ram_resource(dev, 6, remapbasek,
	144	ram_resource(dev, 6, remapbasek,
169	145	(remaplimitk + 64*1024) - remapbasek);
170	146	}
…	…
179	155	}
180	156
181		static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
182		{
183		max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
184		if (max > max_bus) {
185		max_bus = max;
186		}
187		return max;
	157	static u32 e7525_domain_scan_bus(device_t dev, u32 max)
	158	{
	159	max_bus = pci_domain_scan_bus(dev, max);
	160	return max_bus;
188	161	}
189	162
…	…
193	166	.enable_resources = enable_childrens_resources,
194	167	.init = 0,
195		.scan_bus = ~~pci~~_domain_scan_bus,
	168	.scan_bus = e7525_domain_scan_bus,
196	169	.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
197	170	};

trunk/coreboot-v2/src/northbridge/intel/i3100/northbridge.c

r4381	r4394
48	48	resource->flags = IORESOURCE_MEM \| IORESOURCE_CACHEABLE \| \
49	49	IORESOURCE_FIXED \| IORESOURCE_STORED \| IORESOURCE_ASSIGNED;
50		}
51
52
53		~~static void pci_domain_read_resources(device_t dev)~~
54		{
55		~~struct resource *resource;~~
56
57		~~/* Initialize the system wide io space constraints */~~
58		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
59		~~resource->base = 0;~~
60		~~resource->size = 0;~~
61		~~resource->align = 0;~~
62		~~resource->gran = 0;~~
63		~~resource->limit = 0xffffUL;~~
64		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
65
66		~~/* Initialize the system wide memory resources constraints */~~
67		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
68		~~resource->base = 0;~~
69		~~resource->size = 0;~~
70		~~resource->align = 0;~~
71		~~resource->gran = 0;~~
72		~~resource->limit = 0xffffffffUL;~~
73		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
74	50	}
75	51
…	…
200	176	}
201	177
202		static u32 pci_domain_scan_bus(device_t dev, u32 max)
203		{
204		max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
205		if (max > max_bus) {
206		max_bus = max;
207		}
208		return max;
	178	static u32 i3100_domain_scan_bus(device_t dev, u32 max)
	179	{
	180	max_bus = pci_domain_scan_bus(dev, max);
	181	return max_bus;
209	182	}
210	183
…	…
214	187	.enable_resources = enable_childrens_resources,
215	188	.init = 0,
216		.scan_bus = ~~pci~~_domain_scan_bus,
	189	.scan_bus = i3100_domain_scan_bus,
217	190	.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
218	191	};

trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c

r4381	r4394
33	33	.device = 0x7190,
34	34	};
35
36
37		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
38
39		~~static void pci_domain_read_resources(device_t dev)~~
40		{
41		~~struct resource *resource;~~
42
43		~~/* Initialize the system wide io space constraints */~~
44		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
45		~~resource->limit = 0xffffUL;~~
46		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
47
48		~~/* Initialize the system wide memory resources constraints */~~
49		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
50		~~resource->limit = 0xffffffffULL;~~
51		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
52		}
53	35
54	36	static void ram_resource(device_t dev, unsigned long index,
…	…
96	78	#endif
97	79
98		static void ~~pci~~_domain_set_resources(device_t dev)
	80	static void i440bx_domain_set_resources(device_t dev)
99	81	{
100	82	device_t mc_dev;
…	…
141	123	}
142	124
143		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
144		{
145		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
146		~~return max;~~
147		}
148
149	125	static struct device_operations pci_domain_ops = {
150	126	.read_resources = pci_domain_read_resources,
151		.set_resources = ~~pci~~_domain_set_resources,
	127	.set_resources = i440bx_domain_set_resources,
152	128	.enable_resources = enable_childrens_resources,
153	129	.init = 0,

trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c

r4381	r4394
53	53	};
54	54
55		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
56
57		~~static void pci_domain_read_resources(device_t dev)~~
58		{
59		~~struct resource *resource;~~
60		~~unsigned reg;~~
61
62		~~/* Initialize the system wide io space constraints */~~
63		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
64		~~resource->base = 0x400;~~
65		~~resource->limit = 0xffffUL;~~
66		~~resource->flags =~~
67		~~IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
68
69		~~/* Initialize the system wide memory resources constraints */~~
70		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
71		~~resource->limit = 0xffffffffULL;~~
72		~~resource->flags =~~
73		~~IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
74		}
75
76	55	static void ram_resource(device_t dev, unsigned long index,
77	56	unsigned long basek, unsigned long sizek)
…	…
182	161	}
183	162
184		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
185		{
186		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
187		~~return max;~~
188		}
189
190	163	static struct device_operations pci_domain_ops = {
191	164	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/intel/i82830/northbridge.c

r4381	r4394
51	51	.device = 0x3575,
52	52	};
53
54		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
55
56		~~static void pci_domain_read_resources(device_t dev)~~
57		{
58		~~struct resource *resource;~~
59
60		~~/* Initialize the system wide I/O space constraints. */~~
61		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
62		~~resource->limit = 0xffffUL;~~
63		~~resource->flags =~~
64		~~IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
65
66		~~/* Initialize the system wide memory resources constraints. */~~
67		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
68		~~resource->limit = 0xffffffffULL;~~
69		~~resource->flags =~~
70		~~IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
71		}
72	53
73	54	static void ram_resource(device_t dev, unsigned long index,
…	…
159	140	}
160	141
161		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
162		{
163		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
164		~~return max;~~
165		}
166
167	142	static struct device_operations pci_domain_ops = {
168	143	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/intel/i855gme/northbridge.c

r4381	r4394
31	31	#include <cpu/x86/cache.h>
32	32	#include "chip.h"
33
34		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
35
36		~~static void pci_domain_read_resources(device_t dev)~~
37		{
38		~~struct resource *resource;~~
39		~~unsigned reg;~~
40
41		~~/* Initialize the system wide io space constraints */~~
42		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
43		~~resource->limit = 0xffffUL;~~
44		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
45
46		~~/* Initialize the system wide memory resources constraints */~~
47		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
48		~~resource->limit = 0xffffffffULL;~~
49		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
50		}
51	33
52	34	static void ram_resource(device_t dev, unsigned long index,
…	…
157	139	}
158	140
159		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
160		{
161		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
162		~~return max;~~
163		}
164
165	141	static struct device_operations pci_domain_ops = {
166	142	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/intel/i855pm/northbridge.c

r4381	r4394
10	10	#include <bitops.h>
11	11	#include "chip.h"
12
13		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
14
15		~~static void pci_domain_read_resources(device_t dev)~~
16		{
17		~~struct resource *resource;~~
18
19		~~/* Initialize the system wide io space constraints */~~
20		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
21		~~resource->limit = 0xffffUL;~~
22		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
23
24		~~/* Initialize the system wide memory resources constraints */~~
25		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
26		~~resource->limit = 0xffffffffULL;~~
27		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
28		}
29	12
30	13	static void ram_resource(device_t dev, unsigned long index,
…	…
124	107	}
125	108
126		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
127		{
128		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
129		~~return max;~~
130		}
131
132	109	static struct device_operations pci_domain_ops = {
133	110	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c

r4381	r4394
42	42	resource->flags = IORESOURCE_MEM \| IORESOURCE_CACHEABLE \|
43	43	IORESOURCE_FIXED \| IORESOURCE_STORED \| IORESOURCE_ASSIGNED;
44		}
45
46		~~static void pci_domain_read_resources(device_t dev)~~
47		{
48		~~struct resource *resource;~~
49
50		~~/* Initialize the system wide io space constraints */~~
51		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
52		~~resource->base = 0;~~
53		~~resource->size = 0;~~
54		~~resource->align = 0;~~
55		~~resource->gran = 0;~~
56		~~resource->limit = 0xffffUL;~~
57		~~resource->flags =~~
58		~~IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
59
60		~~/* Initialize the system wide memory resources constraints */~~
61		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
62		~~resource->base = 0;~~
63		~~resource->size = 0;~~
64		~~resource->align = 0;~~
65		~~resource->gran = 0;~~
66		~~resource->limit = 0xffffffffUL;~~
67		~~resource->flags =~~
68		~~IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
69	44	}
70	45
…	…
185	160	}
186	161
187		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
188		{
189		~~max = pci_scan_bus(&dev->link[0], 0, 0xff, max);~~
190	162	/* TODO We could determine how many PCIe busses we need in
191	163	* the bar. For now that number is hardcoded to a max of 64.
	164	* See e7525/northbridge.c for an example.
192	165	*/
193		~~return max;~~
194		}
195
196	166	static struct device_operations pci_domain_ops = {
197	167	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/motorola/mpc107/mpc107_northbridge.c

r3053	r4394
17	17	* devices.
18	18	*/
19		static void ~~pci~~_domain_read_resources(device_t dev)
	19	static void mpc107_domain_read_resources(device_t dev)
20	20	{
21	21	struct resource *resource;
…	…
102	102	}
103	103
104
105		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
106		{
107		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
108		~~return max;~~
109		}
110
111	104	static struct device_operations pci_domain_ops = {
112		.read_resources = ~~pci~~_domain_read_resources,
	105	.read_resources = mpc107_domain_read_resources,
113	106	.set_resources = pci_domain_set_resources,
114	107	.enable_resources = enable_childrens_resources,

trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c

r4386	r4394
102	102	};
103	103
104		static void ~~pci~~_domain_read_resources(device_t dev)
	104	static void cn400_domain_read_resources(device_t dev)
105	105	{
106	106	struct resource *resource;
107	107
108		printk_spew("Entering ~~cn400 pci_domain_read_resources.\n"~~);
	108	printk_spew("Entering %s.\n", __func__);
109	109
110	110	/* Initialize the system wide I/O space constraints. */
…	…
120	120	IORESOURCE_ASSIGNED;
121	121
122		printk_spew("Leaving ~~cn400 pci_domain_read_resources.\n"~~);
	122	printk_spew("Leaving %s.\n", __func__);
123	123	}
124	124
…	…
174	174	#endif
175	175
176		static void ~~pci~~_domain_set_resources(device_t dev)
	176	static void cn400_domain_set_resources(device_t dev)
177	177	{
178	178	/* The order is important to find the correct RAM size. */
…	…
181	181	u32 pci_tolm;
182	182
183		printk_spew("Entering ~~cn400 pci_domain_set_resources.\n"~~);
	183	printk_spew("Entering %s.\n", __func__);
184	184
185	185	pci_tolm = find_pci_tolm(&dev->link[0]);
…	…
227	227	assign_resources(&dev->link[0]);
228	228
229		printk_spew("Leaving ~~cn400 pci_domain_set_resources.\n"~~);
230		}
231
232		static unsigned int ~~pci~~_domain_scan_bus(device_t dev, unsigned int max)
233		{
234		printk_debug("Entering ~~cn400 pci_domain_scan_bus.\n"~~);
	229	printk_spew("Leaving %s.\n", __func__);
	230	}
	231
	232	static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
	233	{
	234	printk_debug("Entering %s.\n", __func__);
235	235
236	236	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
…	…
239	239
240	240	static const struct device_operations pci_domain_ops = {
241		.read_resources = ~~pci~~_domain_read_resources,
242		.set_resources = ~~pci~~_domain_set_resources,
	241	.read_resources = cn400_domain_read_resources,
	242	.set_resources = cn400_domain_set_resources,
243	243	.enable_resources = enable_childrens_resources,
244	244	.init = 0,
245		.scan_bus = ~~pci~~_domain_scan_bus,
	245	.scan_bus = cn400_domain_scan_bus,
246	246	};
247	247

trunk/coreboot-v2/src/northbridge/via/cn700/northbridge.c

r4381	r4394
98	98	};
99	99
100		~~static void pci_domain_read_resources(device_t dev)~~
101		{
102		~~struct resource *resource;~~
103
104		~~printk_spew("Entering cn700 pci_domain_read_resources.\n");~~
105
106		~~/* Initialize the system wide I/O space constraints. */~~
107		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
108		~~resource->limit = 0xffffUL;~~
109		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|~~
110		~~IORESOURCE_ASSIGNED;~~
111
112		~~/* Initialize the system wide memory resources constraints. */~~
113		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
114		~~resource->limit = 0xffffffffULL;~~
115		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|~~
116		~~IORESOURCE_ASSIGNED;~~
117
118		~~printk_spew("Leaving cn700 pci_domain_read_resources.\n");~~
119		}
120
121	100	static void ram_resource(device_t dev, unsigned long index,
122	101	unsigned long basek, unsigned long sizek)
…	…
224	203	}
225	204
226		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
227		{
228		~~printk_debug("Entering cn700 pci_domain_scan_bus.\n");~~
229
230		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
231		~~return max;~~
232		}
233
234	205	static const struct device_operations pci_domain_ops = {
235	206	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c

r4126	r4394
330	330	void cx700_read_resources(device_t dev)
331	331	{
332		struct resource *res~~ource~~;
	332	struct resource *res;
333	333
334	334	/* Make sure we call our childrens set/enable functions - these
…	…
338	338	pci_dev_read_resources(dev);
339	339
340		resource = new_resource(dev, 1);
341		resource->flags \|=
342		IORESOURCE_FIXED \| IORESOURCE_ASSIGNED \| IORESOURCE_IO \| IORESOURCE_STORED;
343		resource->size = 2;
344		resource->base = 0x2e;
	340	res = new_resource(dev, 1);
	341	res->base = 0x0UL;
	342	res->size = 0x400UL;
	343	res->limit = 0xffffUL;
	344	res->flags = IORESOURCE_IO \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	345
	346	res = new_resource(dev, 3); /* IOAPIC */
	347	res->base = 0xfec00000;
	348	res->size = 0x00001000;
	349	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
345	350	}
346	351

trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c

r4381	r4394
32	32	#include "chip.h"
33	33	#include "northbridge.h"
34
35		~~static void pci_domain_read_resources(device_t dev)~~
36		{
37		~~struct resource *resource;~~
38
39		~~/* Initialize the system wide io space constraints */~~
40		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
41		~~resource->limit = 0xffffUL;~~
42		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
43
44		~~/* Initialize the system wide memory resources constraints */~~
45		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
46		~~resource->limit = 0xffffffffULL;~~
47		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
48		}
49	34
50	35	static void ram_resource(device_t dev, unsigned long index,
…	…
147	132	}
148	133
149		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
150		{
151		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
152		~~return max;~~
153		}
154
155	134	static struct device_operations pci_domain_ops = {
156	135	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/via/vt8601/northbridge.c

r4381	r4394
45	45	.device = 0x0601, /* 0x8601 is the AGP bridge? */
46	46	};
47
48		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
49
50		~~static void pci_domain_read_resources(device_t dev)~~
51		{
52		~~struct resource *resource;~~
53
54		~~/* Initialize the system wide io space constraints */~~
55		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
56		~~resource->limit = 0xffffUL;~~
57		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
58
59		~~/* Initialize the system wide memory resources constraints */~~
60		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
61		~~resource->limit = 0xffffffffULL;~~
62		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;~~
63		}
64	47
65	48	static void ram_resource(device_t dev, unsigned long index,
…	…
161	144	}
162	145
163		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
164		{
165		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
166		~~return max;~~
167		}
168
169	146	static struct device_operations pci_domain_ops = {
170	147	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/via/vt8623/northbridge.c

r4381	r4394
190	190	.device = 0x3122,
191	191	};
192
193
194		~~#define BRIDGE_IO_MASK (IORESOURCE_IO \| IORESOURCE_MEM)~~
195
196		~~static void pci_domain_read_resources(device_t dev)~~
197		{
198		~~struct resource *resource;~~
199
200		~~printk_spew("Entering vt8623 pci_domain_read_resources.\n");~~
201
202		~~/* Initialize the system wide io space constraints */~~
203		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));~~
204		~~resource->limit = 0xffffUL;~~
205		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|~~
206		~~IORESOURCE_ASSIGNED;~~
207
208		~~/* Initialize the system wide memory resources constraints */~~
209		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));~~
210		~~resource->limit = 0xffffffffULL;~~
211		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|~~
212		~~IORESOURCE_ASSIGNED;~~
213
214		~~printk_spew("Leaving vt8623 pci_domain_read_resources.\n");~~
215		}
216	192
217	193	static void ram_resource(device_t dev, unsigned long index,
…	…
314	290	}
315	291
316		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
317		{
318		~~printk_spew("Entering vt8623 pci_domain_scan_bus.\n");~~
319
320		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
321		~~return max;~~
322		}
323
324	292	static struct device_operations pci_domain_ops = {
325	293	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c

r4314	r4394
70	70	};
71	71
72		~~static void pci_domain_read_resources(device_t dev)~~
73		{
74		~~struct resource *resource;~~
75
76		~~printk_spew("Entering vx800 pci_domain_read_resources.\n");~~
77
78		~~/* Initialize the system wide io space constraints */~~
79		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));~~
80		~~resource->limit = 0xffffUL;~~
81		~~resource->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|~~
82		~~IORESOURCE_ASSIGNED;~~
83
84		~~/* Initialize the system wide memory resources constraints */~~
85		~~resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));~~
86		~~resource->limit = 0xffffffffULL;~~
87		~~resource->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|~~
88		~~IORESOURCE_ASSIGNED;~~
89
90		~~printk_spew("Leaving vx800 pci_domain_read_resources.\n");~~
91		}
92
93	72	static void ram_resource(device_t dev, unsigned long index,
94	73	unsigned long basek, unsigned long sizek)
…	…
196	175	}
197	176
198		~~static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)~~
199		{
200		~~printk_debug("Entering vx800 pci_domain_scan_bus.\n");~~
201
202		~~max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);~~
203		~~return max;~~
204		}
205
206	177	static const struct device_operations pci_domain_ops = {
207	178	.read_resources = pci_domain_read_resources,

trunk/coreboot-v2/src/southbridge/amd/amd8111/amd8111_lpc.c

r4335	r4394
163	163	struct resource *res;
164	164
165		/* Get the normal ~~pci resources of this device~~ */
	165	/* Get the normal PCI resources of this device. */
166	166	pci_dev_read_resources(dev);
167	167
168		/* Add an extra subtractive resource for both memory and I/O */
	168	/* Add an extra subtractive resource for both memory and I/O. */
169	169	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
170		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
171
	170	res->base = 0;
	171	res->size = 0x1000;
	172	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	173	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	174
172	175	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
173		res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	176	res->base = 0xff800000;
	177	res->size = 0x00800000; /* 8 MB for flash */
	178	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	179	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	180
	181	res = new_resource(dev, 3); /* IOAPIC */
	182	res->base = 0xfec00000;
	183	res->size = 0x00001000;
	184	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
174	185	}
175	186

trunk/coreboot-v2/src/southbridge/amd/amd8131/amd8131_bridge.c

r4335	r4394
365	365	dev->command \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
366	366	res->flags \|= IORESOURCE_STORED;
367		~~compute_allocate_resource(&dev->link[0], res,~~
368		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
369		~~IORESOURCE_MEM);~~
370	367	base = res->base;
371	368	end = resource_end(res);

trunk/coreboot-v2/src/southbridge/amd/amd8132/amd8132_bridge.c

r3964	r4394
351	351	dev->command \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
352	352	res->flags \|= IORESOURCE_STORED;
353		~~compute_allocate_resource(&dev->link[0], res,~~
354		~~IORESOURCE_MEM \| IORESOURCE_PREFETCH,~~
355		~~IORESOURCE_MEM);~~
356	353	base = res->base;
357	354	end = resource_end(res);

trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c

r3052	r4394
26	26	#include "cs5530.h"
27	27
	28	static void cs5530_read_resources(device_t dev)
	29	{
	30	struct resource* res;
	31
	32	pci_dev_read_resources(dev);
	33
	34	res = new_resource(dev, 1);
	35	res->base = 0x0UL;
	36	res->size = 0x400UL;
	37	res->limit = 0xffffUL;
	38	res->flags = IORESOURCE_IO \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	39
	40	res = new_resource(dev, 3); /* IOAPIC */
	41	res->base = 0xfec00000;
	42	res->size = 0x00001000;
	43	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	44	}
	45
28	46	static void isa_init(struct device *dev)
29	47	{
…	…
46	64
47	65	static struct device_operations isa_ops = {
48		.read_resources = ~~pci_dev~~_read_resources,
	66	.read_resources = cs5530_read_resources,
49	67	.set_resources = pci_dev_set_resources,
50	68	.enable_resources = cs5530_pci_dev_enable_resources,

trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c

r3943	r4394
70	70	}
71	71
	72	static void cs5535_read_resources(device_t dev)
	73	{
	74	struct resource* res;
	75
	76	pci_dev_read_resources(dev);
	77
	78	res = new_resource(dev, 1);
	79	res->base = 0x0UL;
	80	res->size = 0x400UL;
	81	res->limit = 0xffffUL;
	82	res->flags = IORESOURCE_IO \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	83
	84	res = new_resource(dev, 3); /* IOAPIC */
	85	res->base = 0xfec00000;
	86	res->size = 0x00001000;
	87	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	88	}
	89
72	90	static void cs5535_pci_dev_enable_resources(device_t dev)
73	91	{
…	…
78	96
79	97	static struct device_operations southbridge_ops = {
80		.read_resources = ~~pci_dev~~_read_resources,
	98	.read_resources = cs5535_read_resources,
81	99	.set_resources = pci_dev_set_resources,
82	100	.enable_resources = cs5535_pci_dev_enable_resources,

trunk/coreboot-v2/src/southbridge/amd/cs5536/cs5536.c

r3980	r4394
608	608	}
609	609
	610	static void cs5536_read_resources(device_t dev)
	611	{
	612	struct resource *res;
	613
	614	pci_dev_read_resources(dev);
	615
	616	res = new_resource(dev, 1);
	617	res->base = 0x0UL;
	618	res->size = 0x400UL;
	619	res->limit = 0xffffUL;
	620	res->flags = IORESOURCE_IO \|
	621	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	622
	623	res = new_resource(dev, 3); /* IOAPIC */
	624	res->base = 0xfec00000;
	625	res->size = 0x00001000;
	626	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	627	}
	628
610	629	static void southbridge_enable(struct device *dev)
611	630	{
…	…
622	641
623	642	static struct device_operations southbridge_ops = {
624		.read_resources = ~~pci_dev~~_read_resources,
	643	.read_resources = cs5536_read_resources,
625	644	.set_resources = pci_dev_set_resources,
626	645	.enable_resources = cs5536_pci_dev_enable_resources,

trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_lpc.c

r3785	r4394
71	71	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
72	72
73		/* Add an extra subtractive resource for both memory and I/O */
	73	/* Add an extra subtractive resource for both memory and I/O. */
74	74	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
75		res->flags =
76		IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	75	res->base = 0;
	76	res->size = 0x1000;
	77	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	78	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
77	79
78	80	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
79		res->flags =
80		IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	81	res->base = 0xff800000;
	82	res->size = 0x00800000; /* 8 MB for flash */
	83	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	84	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	85
	86	res = new_resource(dev, 3); /* IOAPIC */
	87	res->base = 0xfec00000;
	88	res->size = 0x00001000;
	89	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
81	90
82	91	compact_resources(dev);
…	…
112	121	child = child->sibling) {
113	122	enable_resources(child);
114		if (child->~~have_resources~~
	123	if (child->enabled
115	124	&& (child->path.type == DEVICE_PATH_PNP)) {
116	125	for (i = 0; i < child->resources; i++) {

trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c

r2891	r4394
30	30	{
31	31	struct resource *res;
32		~~unsigned long index;~~
33	32
34	33	/* Get the normal pci resources of this device */
35		pci_dev_read_resources(dev);
36
37		/* Add an extra subtractive resource for both memory and I/O */
38		res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
39		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
40
41		res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
42		res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	34	pci_dev_read_resources(dev);
43	35
	36	/* Add an extra subtractive resource for both memory and I/O. */
	37	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
	38	res->base = 0;
	39	res->size = 0x1000;
	40	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	41	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	42
	43	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
	44	res->base = 0xff800000;
	45	res->size = 0x00800000; /* 8 MB for flash */
	46	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	47	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	48
	49	res = new_resource(dev, 3); /* IOAPIC */
	50	res->base = 0xfec00000;
	51	res->size = 0x00001000;
	52	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
44	53	}
45	54
…	…
70	79	for (child = dev->link[link].children; child; child = child->sibling) {
71	80	enable_resources(child);
72		if(child->~~have_resources~~ && (child->path.type == DEVICE_PATH_PNP)) {
	81	if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
73	82	for(i=0;i<child->resources;i++) {
74	83	struct resource *res;

trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c

r4335	r4394
52	52	/* Get the normal pci resources of this device */
53	53	pci_dev_read_resources(dev);
54
55	54	/* Get Resource for SMBUS */
56	55	pci_get_resource(dev, 0x90);

trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c

r4335	r4394
362	362	res = pci_get_resource(dev, GPIO_BAR);
363	363
364		/* Add an extra subtractive resource for both memory and I/O */
	364	/* Add an extra subtractive resource for both memory and I/O. */
365	365	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
366		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	366	res->base = 0;
	367	res->size = 0x1000;
	368	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	369	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
367	370
368	371	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
369		res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	372	res->base = 0xff800000;
	373	res->size = 0x00800000; /* 8 MB for flash */
	374	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	375	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	376
	377	res = new_resource(dev, 3); /* IOAPIC */
	378	res->base = 0xfec00000;
	379	res->size = 0x00001000;
	380	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
370	381	}
371	382

trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c

r4392	r4394
400	400	res = pci_get_resource(dev, GPIO_BAR);
401	401
402		/* Add an extra subtractive resource for both memory and I/O */
	402	/* Add an extra subtractive resource for both memory and I/O. */
403	403	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
404		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	404	res->base = 0;
	405	res->size = 0x1000;
	406	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	407	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
405	408
406	409	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
407		res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	410	res->base = 0xff800000;
	411	res->size = 0x00800000; /* 8 MB for flash */
	412	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	413	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	414
	415	res = new_resource(dev, 3); /* IOAPIC */
	416	res->base = 0xfec00000;
	417	res->size = 0x00001000;
	418	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
408	419
409	420	/* Add resource for RCBA */

trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c

r4269	r4394
56	56	}
57	57
58		static const struct device_operations isa_ops = {
59		.read_resources = pci_dev_read_resources,
	58	static void sb_read_resources(struct device *dev)
	59	{
	60	struct resource *res;
	61
	62	pci_dev_read_resources(dev);
	63
	64	res = new_resource(dev, 1);
	65	res->base = 0x0UL;
	66	res->size = 0x1000UL;
	67	res->limit = 0xffffUL;
	68	res->flags = IORESOURCE_IO \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	69
	70	res = new_resource(dev, 2);
	71	res->base = 0xff800000UL;
	72	res->size = 0x00800000UL; /* 8 MB for flash */
	73	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	74
	75	res = new_resource(dev, 3); /* IOAPIC */
	76	res->base = 0xfec00000;
	77	res->size = 0x00001000;
	78	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	79	}
	80
	81	const struct device_operations isa_ops = {
	82	.read_resources = sb_read_resources,
60	83	.set_resources = pci_dev_set_resources,
61	84	.enable_resources = pci_dev_enable_resources,

trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_lpc.c

r4381	r4394
208	208	struct resource *res;
209	209
210		/* Get the normal ~~pci resources of this device~~ */
	210	/* Get the normal PCI resources of this device. */
211	211	pci_dev_read_resources(dev);
212	212
213		/* Add an extra subtractive resource for both memory and I/O */
	213	/* Add an extra subtractive resource for both memory and I/O. */
214	214	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
215		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	215	res->base = 0;
	216	res->size = 0x1000;
	217	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	218	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
216	219
217	220	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
218		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	221	res->base = 0xff800000;
	222	res->size = 0x00800000; /* 8 MB for flash */
	223	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	224	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	225
	226	res = new_resource(dev, 3); /* IOAPIC */
	227	res->base = 0xfec00000;
	228	res->size = 0x00001000;
	229	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
219	230	}
220	231

trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c

r4340	r4394
183	183	struct resource *res;
184	184
185		/* Get the normal ~~pci resources of this device~~ */
	185	/* Get the normal PCI resources of this device. */
186	186	pci_dev_read_resources(dev);
187	187
188		/* Add an extra subtractive resource for both memory and I/O */
	188	/* Add an extra subtractive resource for both memory and I/O. */
189	189	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
190		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	190	res->base = 0;
	191	res->size = 0x1000;
	192	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	193	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
191	194
192	195	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
193		res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	196	res->base = 0xff800000;
	197	res->size = 0x00800000; /* 8 MB for flash */
	198	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	199	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	200
	201	res = new_resource(dev, 3); /* IOAPIC */
	202	res->base = 0xfec00000;
	203	res->size = 0x00001000;
	204	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
194	205	}
195	206

trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_lpc.c

r4381	r4394
335	335	struct resource *res;
336	336
337		/* Get the normal ~~pci resources of this device~~ */
	337	/* Get the normal PCI resources of this device. */
338	338	pci_dev_read_resources(dev);
339	339
…	…
344	344	res = pci_get_resource(dev, GPIO_BAR);
345	345
346		/* Add an extra subtractive resource for both memory and I/O */
	346	/* Add an extra subtractive resource for both memory and I/O. */
347	347	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
348		res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	348	res->base = 0;
	349	res->size = 0x1000;
	350	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	351	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
349	352
350	353	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
351		res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	354	res->base = 0xff800000;
	355	res->size = 0x00800000; /* 8 MB for flash */
	356	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	357	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	358
	359	res = new_resource(dev, 3); /* IOAPIC */
	360	res->base = 0xfec00000;
	361	res->size = 0x00001000;
	362	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
352	363	}
353	364

trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c

r4381	r4394
420	420	/* Add an extra subtractive resource for both memory and I/O. */
421	421	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
422		res->flags =
423		IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	422	res->base = 0;
	423	res->size = 0x1000;
	424	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	425	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
424	426
425	427	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
426		res->flags =
427		IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	428	res->base = 0xff800000;
	429	res->size = 0x00800000; /* 8 MB for flash */
	430	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	431	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	432
	433	res = new_resource(dev, 3); /* IOAPIC */
	434	res->base = 0xfec00000;
	435	res->size = 0x00001000;
	436	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
428	437	}
429	438

trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c

r4335	r4394
341	341	/* Add an extra subtractive resource for both memory and I/O. */
342	342	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
343		res->flags =
344		IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	343	res->base = 0;
	344	res->size = 0x1000;
	345	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	346	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
345	347
346	348	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
347		res->flags =
348		IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	349	res->base = 0xff800000;
	350	res->size = 0x00800000; /* 8 MB for flash */
	351	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	352	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	353
	354	res = new_resource(dev, 3); /* IOAPIC */
	355	res->base = 0xfec00000;
	356	res->size = 0x00001000;
	357	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
349	358	}
350	359

trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c

r4381	r4394
276	276	/* Add an extra subtractive resource for both memory and I/O. */
277	277	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
278		res->flags =
279		IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	278	res->base = 0;
	279	res->size = 0x1000;
	280	res->flags = IORESOURCE_IO \| IORESOURCE_SUBTRACTIVE \|
	281	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
280	282
281	283	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
282		res->flags =
283		IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \| IORESOURCE_ASSIGNED;
	284	res->base = 0xff800000;
	285	res->size = 0x00800000; /* 8 MB for flash */
	286	res->flags = IORESOURCE_MEM \| IORESOURCE_SUBTRACTIVE \|
	287	IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
	288
	289	res = new_resource(dev, 3); /* IOAPIC */
	290	res->base = 0xfec00000;
	291	res->size = 0x00001000;
	292	res->flags = IORESOURCE_MEM \| IORESOURCE_ASSIGNED \| IORESOURCE_FIXED;
284	293	}
285	294
…	…
309	318	for (child = dev->link[link].children; child; child = child->sibling) {
310	319	enable_resources(child);
311		if (child->~~have_resources~~ && (child->path.type == DEVICE_PATH_PNP)) {
	320	if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
312	321	for (i = 0; i < child->resources; i++) {
313	322	struct resource *res;

trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c

r3631	r4394
6	6	#include <console/console.h>
7	7	#include <device/device.h>
	8	#include <device/resource.h>
8	9	#include <device/pci.h>
9	10	#include <device/pci_ids.h>
…	…
14	15	{
15	16	uint32_t dword;
16		~~#if CONFIG_PCI_64BIT_PREF_MEM == 1~~
17	17	device_t pci_domain_dev;
18		struct resource mem1, mem2;
19		#endif
	18	struct resource mem, pref;
20	19
21	20	dword = pci_read_config32(dev, 0x04);
…	…
37	36	#endif
38	37
39		~~#if CONFIG_PCI_64BIT_PREF_MEM == 1~~
40	38	pci_domain_dev = dev->bus->dev;
41	39	while (pci_domain_dev) {
…	…
48	46	return; /* Impossible */
49	47
50		mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
51		mem2 = find_resource(pci_domain_dev, 2); // mem
52		if (mem1->base > mem2->base) {
53		dword = mem2->base & (0xffff0000UL);
54		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
	48	pref = probe_reso

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