Changeset 4357

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Timestamp:
06/16/09 17:02:52 (9 months ago)
Author:
rminnich
Message:

These changes implement car in qemu. The implementation is in several
ways superior to v3, while lacking its completeness. But, one nice
thing: no more included .S or .c files. It's all separate compilation.
That should allow our Makefiles to work much better.

Note that the current non-CAR implementation is the default and
continues to work (tested FILO boot to Linux on both CAR and non-CAR).

Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that
depend on this variable are grouped in one if, and the other parts
(romcc etc.) are in the else. This change is a model of how we should be
able to do other motherboards.

Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options.

Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file.

Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3.

Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem.

Index: src/pc80/serial.c
make uart_init non-static.

Index: src/pc80/Config.lb
add initobject

Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3.

Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init.

Index: src/arch/i386/init/car.S
generic i386 car code from v3.

Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section.

Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well
get all the debugging we can.

Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds.

Signed-off-by: Ronald G. minnich <rminnich@…>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@…>

Location:
trunk/coreboot-v2
Files:
5 added
8 modified

Legend:

Unmodified
Added
Removed

  • trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb

    r4315 r4357  
    4747                *(.rom.data); 
    4848                *(.init.rodata.*); 
     49                *(.init.text); 
    4950                *(.rodata.*); 
    5051                *(.rom.data.*); 

  • trunk/coreboot-v2/src/lib/Config.lb

    r4320 r4357  
    2121makedefine .PHONY : version.o 
    2222 
    23 initobject uart8250.c 
     23initobject uart8250.o 
    2424initobject memset.o 
    2525initobject memcpy.o 

  • trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb

    r4344 r4357  
     1## we don't use USE_DCACHE_RAM by default 
     2default USE_DCACHE_RAM=0 
    13## 
    24## Compute the location and size of where this firmware image 
    … …  
    4345#object reset.o 
    4446 
     47 
     48## ALL dependencies for USE_DCACHE_RAM go here.  
     49## That way, later, we can simply yank them if we wish.  
     50## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case.  
     51## we do not use failover yet in this case. This is a work in progress.  
     52if USE_DCACHE_RAM 
     53        ## 
     54        ## 
     55        mainboardinit arch/i386/init/entry.S 
     56        mainboardinit arch/i386/init/car.S 
     57        ldscript  /arch/i386/init/ldscript.ld 
     58 
     59        ## The main code for the rom section is called rom.c 
     60        initobject rom.o 
     61else 
     62        ## 
     63        ## Romcc output 
     64        ## 
     65        makerule ./failover.E 
     66                depends "$(MAINBOARD)/failover.c ../romcc"  
     67                action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" 
     68        end 
     69         
     70        makerule ./failover.inc 
     71                depends "$(MAINBOARD)/failover.c ../romcc" 
     72                action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" 
     73        end 
     74         
     75        makerule ./auto.E  
     76                depends "$(MAINBOARD)/auto.c option_table.h ../romcc"  
     77                action  "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" 
     78        end 
     79        makerule ./auto.inc  
     80                depends "$(MAINBOARD)/auto.c option_table.h ../romcc" 
     81                action  "../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" 
     82        end 
     83         
     84        ## 
     85        ## Build our 16 bit and 32 bit coreboot entry code 
     86        ## 
     87        mainboardinit cpu/x86/16bit/entry16.inc 
     88        mainboardinit cpu/x86/32bit/entry32.inc 
     89        ldscript /cpu/x86/16bit/entry16.lds 
     90        ldscript /cpu/x86/32bit/entry32.lds 
     91 
     92        ## 
     93        ## Build our reset vector (This is where coreboot is entered) 
     94        ## 
     95        mainboardinit cpu/x86/16bit/reset16.inc  
     96        ldscript /cpu/x86/16bit/reset16.lds  
     97         
     98        ### Should this be in the northbridge code? 
     99        mainboardinit arch/i386/lib/cpu_reset.inc 
     100 
     101        ## 
     102        ## Setup RAM 
     103        ## 
     104        mainboardinit cpu/x86/fpu/enable_fpu.inc 
     105        mainboardinit ./auto.inc 
     106         
     107        ## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.  
     108        ## 
     109        ## Include an id string (For safe flashing) 
     110        ## 
     111        mainboardinit arch/i386/lib/id.inc 
     112        ldscript /arch/i386/lib/id.lds 
     113         
    45114## 
    46 ## Romcc output 
     115## end of USE_DCACHE_RAM bits.  
    47116## 
    48 makerule ./failover.E 
    49         depends "$(MAINBOARD)/failover.c ../romcc"  
    50         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" 
    51117end 
    52  
    53 makerule ./failover.inc 
    54         depends "$(MAINBOARD)/failover.c ../romcc" 
    55         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" 
    56 end 
    57  
    58 makerule ./auto.E  
    59         depends "$(MAINBOARD)/auto.c option_table.h ../romcc"  
    60         action  "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" 
    61 end 
    62 makerule ./auto.inc  
    63         depends "$(MAINBOARD)/auto.c option_table.h ../romcc" 
    64         action  "../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" 
    65 end 
    66  
    67 ## 
    68 ## Build our 16 bit and 32 bit coreboot entry code 
    69 ## 
    70 mainboardinit cpu/x86/16bit/entry16.inc 
    71 mainboardinit cpu/x86/32bit/entry32.inc 
    72 ldscript /cpu/x86/16bit/entry16.lds 
    73 ldscript /cpu/x86/32bit/entry32.lds 
    74  
    75 ## 
    76 ## Build our reset vector (This is where coreboot is entered) 
    77 ## 
    78 mainboardinit cpu/x86/16bit/reset16.inc  
    79 ldscript /cpu/x86/16bit/reset16.lds  
    80  
    81 ### Should this be in the northbridge code? 
    82 mainboardinit arch/i386/lib/cpu_reset.inc 
    83  
    84 ## 
    85 ## Include an id string (For safe flashing) 
    86 ## 
    87 mainboardinit arch/i386/lib/id.inc 
    88 ldscript /arch/i386/lib/id.lds 
    89  
    90 ### 
    91 ### O.k. We aren't just an intermediary anymore! 
    92 ### 
    93  
    94 ## 
    95 ## Setup RAM 
    96 ## 
    97 mainboardinit cpu/x86/fpu/enable_fpu.inc 
    98 mainboardinit ./auto.inc 
    99118 
    100119## 

  • trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb

    r4344 r4357  
    4242uses CONFIG_CONSOLE_SERIAL8250 
    4343uses USE_DCACHE_RAM 
    44  
     44uses DCACHE_RAM_BASE 
     45uses DCACHE_RAM_SIZE 
     46uses CONFIG_USE_INIT 
     47uses CONFIG_USE_PRINTK_IN_CAR 
    4548 
    4649uses DEFAULT_CONSOLE_LOGLEVEL 
    … …  
    129132default HOSTCC="gcc" 
    130133 
     134## 
     135## known-good settings for qemu 
     136default DCACHE_RAM_BASE=0x8f000 
     137default DCACHE_RAM_SIZE=0x1000 
     138 
     139 
     140 
     141 
    131142end 

  • trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/failover.c

    r1734 r4357  
    1 #define ASSEMBLY 1 
    21#include <stdint.h> 
    32#include <device/pci_def.h> 
    … …  
    54#include <arch/io.h> 
    65#include "arch/romcc_io.h" 
    7 #include "pc80/mc146818rtc_early.c" 
    8 #include "cpu/x86/lapic/boot_cpu.c" 
     6/* no code inclusion allowed */ 
     7//#include "pc80/mc146818rtc_early.c" 
     8//#include "cpu/x86/lapic/boot_cpu.c" 
    99 
    1010static void main(void) 
    1111{ 
    12   /* for now, just always assume failure */ 
    13  
    1412#if 0 
    1513        /* Is this a cpu reset? */ 
    … …  
    2826#endif 
    2927} 
     28 

  • trunk/coreboot-v2/src/pc80/Config.lb

    r4321 r4357  
    1818 
    1919object keyboard.o 
     20 
     21if CONFIG_USE_INIT 
     22        initobject serial.o 
     23end 

  • trunk/coreboot-v2/src/pc80/serial.c

    r4233 r4357  
    9797 
    9898extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); 
    99 static void uart_init(void) 
     99void uart_init(void) 
    100100{ 
    101101#if USE_OPTION_TABLE == 1 

  • trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb

    r4344 r4357  
    1010option HAVE_PIRQ_TABLE=1 
    1111option IRQ_SLOT_COUNT=6 
     12option DEFAULT_CONSOLE_LOGLEVEL=9 
     13option MAXIMUM_CONSOLE_LOGLEVEL=9 
    1214 
    1315romimage "normal"