Changeset 3764

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Timestamp:
11/21/08 00:18:10 (7 weeks ago)
Author:
uwe
Message:

Get rid of the unnecessary indirection by 'struct mem_controller' for the
Intel 810 chipset (and all boards using it). This isn't required for this
chipset as there's only one memory controller.

This also helps a lot with romcc register usage, you should see the dreaded
"too few registers" less often.

Build-tested with all three boards using the Intel 810 chipset.

Signed-off-by: Uwe Hermann <uwe@…>
Acked-by: Corey Osgood <corey.osgood@…>

Location:
trunk/coreboot-v2/src
Files:
6 modified

Legend:

Unmodified
Added
Removed

  • trunk/coreboot-v2/src/mainboard/asus/mew-am/auto.c

    r3653 r3764  
    4949#include "northbridge/intel/i82810/raminit.c" 
    5050/* #include "northbridge/intel/i82810/debug.c" */ 
    51 #include "sdram/generic_sdram.c" 
    5251 
    5352static void main(unsigned long bist) 
    5453{ 
    55         static const struct mem_controller memctrl[] = { 
    56                 { 
    57                         .d0 = PCI_DEV(0, 0, 0), 
    58                         .channel0 = {0x50, 0x51}, 
    59                 } 
    60         }; 
    61  
    6254        if (bist == 0) 
    6355                early_mtrr_init(); 
    … …  
    6860        report_bist_failure(bist); 
    6961        enable_smbus(); 
    70         /* dump_spd_registers(&memctrl[0]); */ 
    71         sdram_initialize(ARRAY_SIZE(memctrl), memctrl); 
     62        /* dump_spd_registers(); */ 
     63        sdram_set_registers(); 
     64        sdram_set_spd_registers(); 
     65        sdram_enable(); 
    7266        /* ram_check(0, 640 * 1024); */ 
    7367} 

  • trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c

    r3742 r3764  
    5353#include "northbridge/intel/i82810/raminit.c" 
    5454#include "northbridge/intel/i82810/debug.c" 
    55 #include "sdram/generic_sdram.c" 
    5655 
    5756static void main(unsigned long bist) 
    5857{ 
    59         static const struct mem_controller memctrl[] = { 
    60                 { 
    61                  .d0 = PCI_DEV(0, 0, 0), 
    62                  .channel0 = {0x50, 0x51}, 
    63                  } 
    64         }; 
    65  
    6658        if (bist == 0) 
    6759                early_mtrr_init(); 
    … …  
    7668        report_bist_failure(bist); 
    7769 
    78         /* dump_spd_registers(&memctrl[0]); */ 
     70        /* dump_spd_registers(); */ 
    7971 
    80         /* sdram_initialize() runs out of registers. */ 
    81         /* sdram_initialize(ARRAY_SIZE(memctrl), memctrl); */ 
    82  
    83         sdram_set_registers(memctrl); 
    84         sdram_set_spd_registers(memctrl); 
    85         sdram_enable(0, memctrl); 
     72        sdram_set_registers(); 
     73        sdram_set_spd_registers(); 
     74        sdram_enable(); 
    8675 
    8776        /* Check RAM. */ 

  • trunk/coreboot-v2/src/mainboard/msi/ms6178/auto.c

    r3742 r3764  
    3838#include "pc80/udelay_io.c" 
    3939#include "northbridge/intel/i82810/raminit.c" 
    40 #include "sdram/generic_sdram.c" 
    4140 
    4241#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) 
    … …  
    4443static void main(unsigned long bist) 
    4544{ 
    46         static const struct mem_controller memctrl[] = { 
    47                 { 
    48                         .d0 = PCI_DEV(0, 0, 0), 
    49                         .channel0 = {0x50, 0x51}, 
    50                 } 
    51         }; 
    52  
    5345        if (bist == 0) 
    5446                early_mtrr_init(); 
    … …  
    6759 
    6860        report_bist_failure(bist); 
    69         /* dump_spd_registers(&memctrl[0]); */ 
    70         sdram_initialize(ARRAY_SIZE(memctrl), memctrl); 
     61 
     62        /* dump_spd_registers(); */ 
     63        sdram_set_registers(); 
     64        sdram_set_spd_registers(); 
     65        sdram_enable(); 
    7166        /* ram_check(0, 640 * 1024); */ 
    7267} 

  • trunk/coreboot-v2/src/northbridge/intel/i82810/debug.c

    r2720 r3764  
    11 
    2 static void dump_spd_registers(const struct mem_controller *ctrl) 
     2static void dump_spd_registers(void) 
    33{ 
    44        int i; 
    55        print_debug("\r\n"); 
    6         for(i = 0; i < 4; i++) { 
     6        for(i = 0; i < DIMM_SOCKETS; i++) { 
    77                unsigned device; 
    8                 device = ctrl->channel0[i]; 
     8                device = DIMM_SPD_BASE + i; 
    99                if (device) { 
    1010                        int j; 

  • trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c

    r3759 r3764  
    6363 * Send the specified RAM command to all DIMMs. 
    6464 * 
    65  * @param Memory controller 
    6665 * @param TODO 
    6766 * @param TODO 
    6867 */ 
    69 static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, 
    70                            uint32_t addr_offset, uint32_t row_offset) 
     68static void do_ram_command(uint32_t command, uint32_t addr_offset, 
     69                           uint32_t row_offset) 
    7170{ 
    7271        uint8_t reg; 
    … …  
    7574 
    7675        /* Configure the RAM command. */ 
    77         reg = pci_read_config8(ctrl->d0, DRAMT); 
     76        reg = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT); 
    7877        reg &= 0x1f;            /* Clear bits 7-5. */ 
    7978        reg |= command << 5; 
    80         pci_write_config8(ctrl->d0, DRAMT, reg); 
     79        pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg); 
    8180 
    8281        /* RAM_COMMAND_NORMAL affects only the memory controller and 
    … …  
    102101 * Set DRP - DRAM Row Population Register (Device 0). 
    103102 */ 
    104 static void spd_set_dram_size(const struct mem_controller *ctrl, 
    105                               uint32_t row_offset) 
     103static void spd_set_dram_size(uint32_t row_offset) 
    106104{ 
    107105        /* The variables drp and dimm_size have to be ints since all the 
    … …  
    114112        for (i = 0; i < DIMM_SOCKETS; i++) { 
    115113                /* First check if a DIMM is actually present. */ 
    116                 if (smbus_read_byte(ctrl->channel0[i], 2) == 4) { 
     114                if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) { 
    117115                        print_debug("Found DIMM in slot "); 
    118116                        print_debug_hex8(i); 
    119117                        print_debug("\r\n"); 
    120118 
    121                         dimm_size = smbus_read_byte(ctrl->channel0[i], 31); 
     119                        dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31); 
    122120 
    123121                        /* WISHLIST: would be nice to display it as decimal? */ 
    … …  
    182180                        /* If the DIMM is dual-sided, the DRP value is +2 */ 
    183181                        /* TODO: Figure out asymetrical configurations. */ 
    184                         if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) == 
     182                        if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) == 
    185183                            0xff) { 
    186184                                print_debug("DIMM is dual-sided\r\n"); 
    … …  
    204202        print_debug("\r\n"); 
    205203 
    206         pci_write_config8(ctrl->d0, DRP, drp); 
    207 } 
    208  
    209 static void set_dram_timing(const struct mem_controller *ctrl) 
     204        pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp); 
     205} 
     206 
     207static void set_dram_timing(void) 
    210208{ 
    211209        /* TODO, for now using default, hopefully safe values. */ 
    212         // pci_write_config8(ctrl->d0, DRAMT, 0x00); 
     210        // pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, 0x00); 
    213211} 
    214212 
    … …  
    240238 * 0x0001   512MB   0xff   256MB dual-sided     256MB dual-sided 
    241239 */ 
    242 static void set_dram_buffer_strength(const struct mem_controller *ctrl) 
    243 { 
    244         pci_write_config16(ctrl->d0, BUFF_SC, 0x77da); 
     240static void set_dram_buffer_strength(void) 
     241{ 
     242        pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, 0x77da); 
    245243} 
    246244 
    … …  
    251249/** 
    252250 * TODO. 
    253  * 
    254  * @param Memory controller 
    255  */ 
    256 static void sdram_set_registers(const struct mem_controller *ctrl) 
     251 */ 
     252static void sdram_set_registers(void) 
    257253{ 
    258254        unsigned long val; 
    259255 
    260256        /* TODO */ 
    261         pci_write_config8(ctrl->d0, GMCHCFG, 0x60); 
     257        pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, 0x60); 
    262258 
    263259        /* PAMR: Programmable Attributes Register 
    … …  
    276272 
    277273        /* Ideally, this should be R/W for as many ranges as possible. */ 
    278         pci_write_config8(ctrl->d0, PAM, 0xff); 
     274        pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0xff); 
    279275 
    280276        /* Enabling the VGA Framebuffer currently screws up the rest of the boot. 
    … …  
    282278         
    283279        /* Enable 1MB framebuffer. */ 
    284         //pci_write_config8(ctrl->d0, SMRAM, 0xC0); 
    285  
    286         //val = pci_read_config16(ctrl->d0, MISSC); 
     280        //pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, 0xC0); 
     281 
     282        //val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC); 
    287283        /* Preserve reserved bits. */ 
    288284        //val &= 0xff06; 
    289285        /* Set graphics cache window to 32MB, no power throttling. */ 
    290286        //val |= 0x0001; 
    291         //pci_write_config16(ctrl->d0, MISSC, val); 
    292  
    293         //val = pci_read_config8(ctrl->d0, MISSC2); 
     287        //pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val); 
     288 
     289        //val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2); 
    294290        /* Enable graphics palettes and clock gating (not optional!) */ 
    295291        //val |= 0x06; 
    296         //pci_write_config8(ctrl->d0, MISSC2, val); 
     292        //pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val); 
    297293} 
    298294 
    299295/** 
    300296 * TODO. 
    301  * 
    302  * @param Memory controller 
    303  */ 
    304 static void sdram_set_spd_registers(const struct mem_controller *ctrl) 
     297 */ 
     298static void sdram_set_spd_registers(void) 
    305299{ 
    306300        /* spd_set_dram_size() moved into sdram_enable() to prevent having 
    307301         * to pass a variable between here and there. 
    308302         */ 
    309         set_dram_buffer_strength(ctrl); 
    310  
    311         set_dram_timing(ctrl); 
     303        set_dram_buffer_strength(); 
     304 
     305        set_dram_timing(); 
    312306} 
    313307 
    314308/** 
    315309 * Enable SDRAM. 
    316  * 
    317  * @param Number of controllers 
    318  * @param Memory controller 
    319  */ 
    320 static void sdram_enable(int controllers, const struct mem_controller *ctrl) 
     310 */ 
     311static void sdram_enable(void) 
    321312{ 
    322313        int i; 
    … …  
    328319        uint32_t row_offset; 
    329320 
    330         spd_set_dram_size(ctrl, row_offset); 
     321        spd_set_dram_size(row_offset); 
    331322 
    332323        /* 1. Apply NOP. */ 
    333324        PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); 
    334         do_ram_command(ctrl, RAM_COMMAND_NOP, 0, row_offset); 
     325        do_ram_command(RAM_COMMAND_NOP, 0, row_offset); 
    335326        udelay(200); 
    336327 
    337328        /* 2. Precharge all. Wait tRP. */ 
    338329        PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); 
    339         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0, row_offset); 
     330        do_ram_command(RAM_COMMAND_PRECHARGE, 0, row_offset); 
    340331        udelay(1); 
    341332 
    342333        /* 3. Perform 8 refresh cycles. Wait tRC each time. */ 
    343334        PRINT_DEBUG("RAM Enable 3: CBR\r\n"); 
    344         do_ram_command(ctrl, RAM_COMMAND_CBR, 0, row_offset); 
     335        do_ram_command(RAM_COMMAND_CBR, 0, row_offset); 
    345336        for (i = 0; i < 8; i++) { 
    346337                read32(0); 
    … …  
    351342        /* 4. Mode register set. Wait two memory cycles. */ 
    352343        PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); 
    353         do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0, row_offset); 
     344        do_ram_command(RAM_COMMAND_MRS, 0x1d0, row_offset); 
    354345        udelay(2); 
    355346 
    356347        /* 5. Normal operation (enables refresh) */ 
    357348        PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); 
    358         do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0, row_offset); 
     349        do_ram_command(RAM_COMMAND_NORMAL, 0, row_offset); 
    359350        udelay(1); 
    360351 

  • trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.h

    r3052 r3764  
    2525#define DIMM_SOCKETS    2 
    2626 
    27 struct mem_controller { 
    28         device_t d0; 
    29         uint16_t channel0[DIMM_SOCKETS]; 
    30 }; 
     27/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ 
     28#define DIMM_SPD_BASE 0x50 
    3129 
    3230/* The following table has been bumped over to this header to avoid clutter in