Changeset 3761
- Timestamp:
- 11/19/08 14:42:14 (7 weeks ago)
- Location:
- trunk/coreboot-v2
- Files:
-
- 7 modified
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src/mainboard/lippert/roadrunner-lx/Config.lb (modified) (7 diffs)
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src/mainboard/lippert/roadrunner-lx/Options.lb (modified) (7 diffs)
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src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c (modified) (5 diffs)
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src/mainboard/lippert/roadrunner-lx/chip.h (modified) (3 diffs)
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src/mainboard/lippert/roadrunner-lx/irq_tables.c (modified) (4 diffs)
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src/mainboard/lippert/roadrunner-lx/mainboard.c (modified) (4 diffs)
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targets/lippert/roadrunner-lx/Config.lb (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb
r3760 r3761 3 3 ## 4 4 ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH 5 ##6 ## Based on Config.lb from AMD's DB800 and DBM690T mainboards.7 5 ## 8 6 ## This program is free software; you can redistribute it and/or modify … … 21 19 ## 22 20 21 ## Based on Config.lb from AMD's DB800 and DBM690T mainboards. 22 23 23 ## 24 24 ## Compute the location and size of where this firmware image … … 27 27 if USE_FALLBACK_IMAGE 28 28 default ROM_SECTION_SIZE = FALLBACK_SIZE 29 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE)29 default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) 30 30 else 31 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE)31 default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) 32 32 default ROM_SECTION_OFFSET = 0 33 33 end … … 39 39 40 40 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 41 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE)41 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) 42 42 43 43 ## 44 44 ## Compute where this copy of coreboot will start in the boot rom 45 45 ## 46 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)46 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) 47 47 48 48 ## … … 53 53 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE 54 54 ## 55 default XIP_ROM_SIZE =6553656 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)55 default XIP_ROM_SIZE = 64 * 1024 56 default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) 57 57 58 58 … … 74 74 75 75 if USE_DCACHE_RAM 76 # compile cache_as_ram.c to auto.inc76 # compile cache_as_ram.c to auto.inc 77 77 makerule ./cache_as_ram_auto.inc 78 79 80 81 78 depends "$(MAINBOARD)/cache_as_ram_auto.c" 79 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" 80 action "perl -e 's/.rodata/.rom.data/g' -pi $@" 81 action "perl -e 's/.text/.section .rom.text/g' -pi $@" 82 82 end 83 83 end … … 137 137 138 138 ## 139 ## Include the secondary Configuration files139 ## Include the secondary configuration files 140 140 ## 141 141 dir /pc80 142 142 config chip.h 143 register "sio_gp1x_config" = "0x20" # bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED 143 144 # Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED. 145 register "sio_gp1x_config" = "0x20" 144 146 145 147 chip northbridge/amd/lx 146 device pci_domain 0 on 147 device pci 1.0 on end # Northbridge 148 device pci 1.1 on end # Graphics 149 device pci 1.2 on end # AES 150 chip southbridge/amd/cs5536 151 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK 152 # SIRQ Mode = Active(Quiet) mode. Save power.... 153 # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK 154 register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 155 register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above 156 register "lpc_serirq_mode" = "1" 157 register "enable_gpio_int_route" = "0x0D0C0700" 158 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash 159 register "enable_USBP4_device" = "0" # 0: host, 1:device 160 register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) 161 register "com1_enable" = "0" 162 register "com1_address" = "0x3E8" 163 register "com1_irq" = "6" 164 register "com2_enable" = "0" 165 register "com2_address" = "0x2E8" 166 register "com2_irq" = "6" 167 register "unwanted_vpci[0]" = "0" # End of list has a zero 168 device pci 8.0 on end # Slot4 169 device pci 9.0 on end # Slot3 170 device pci a.0 on end # Slot2 171 device pci b.0 on end # Slot1 172 device pci c.0 on end # IT8888 173 device pci e.0 on end # Ethernet 174 device pci f.0 on # ISA Bridge 175 chip superio/ite/it8712f 176 device pnp 2e.0 off # Floppy 177 io 0x60 = 0x3f0 178 irq 0x70 = 6 179 drq 0x74 = 2 180 end 181 device pnp 2e.1 on # Com1 182 io 0x60 = 0x3f8 183 irq 0x70 = 4 184 end 185 device pnp 2e.2 on # Com2 186 io 0x60 = 0x2f8 187 irq 0x70 = 3 188 end 189 device pnp 2e.3 on # Parallel Port 190 io 0x60 = 0x378 191 irq 0x70 = 7 192 end 193 device pnp 2e.4 on # EC 194 io 0x60 = 0x290 195 io 0x62 = 0x230 196 irq 0x70 = 9 197 end 198 device pnp 2e.5 on # Keyboard 199 io 0x60 = 0x60 200 io 0x62 = 0x64 201 irq 0x70 = 1 202 end 203 device pnp 2e.6 on # Mouse 204 irq 0x70 = 12 205 end 206 device pnp 2e.7 on # GPIO 207 io 0x62 = 0x1220 208 #io 0x64 = 0x1200 209 end 210 device pnp 2e.8 off # MIDI 211 io 0x60 = 0x300 212 irq 0x70 = 9 213 end 214 device pnp 2e.9 off # GAME 215 io 0x60 = 0x220 216 end 217 device pnp 2e.a off end # CIR 218 end 219 end 220 device pci f.2 on end # IDE Controller 221 device pci f.3 on end # Audio 222 device pci f.4 on end # OHCI 223 device pci f.5 on end # EHCI 224 end 225 end 226 # APIC cluster is late CPU init. 227 device apic_cluster 0 on 228 chip cpu/amd/model_lx 229 device apic 0 on end 230 end 231 end 232 end 148 device pci_domain 0 on 149 device pci 1.0 on end # Northbridge 150 device pci 1.1 on end # Graphics 151 device pci 1.2 on end # AES 152 chip southbridge/amd/cs5536 # Southbridge 153 # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK 154 # SIRQ Mode = Active(Quiet) mode. Save power... 155 # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, 156 # UARTs, etc IRQs. OK 157 register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 158 register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above 159 register "lpc_serirq_mode" = "1" 160 register "enable_gpio_int_route" = "0x0D0C0700" 161 register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash 162 register "enable_USBP4_device" = "0" # 0: host, 1:device 163 register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) 164 register "com1_enable" = "0" 165 register "com1_address" = "0x3E8" 166 register "com1_irq" = "6" 167 register "com2_enable" = "0" 168 register "com2_address" = "0x2E8" 169 register "com2_irq" = "6" 170 register "unwanted_vpci[0]" = "0" # End of list has a zero 171 device pci 8.0 on end # Slot4 172 device pci 9.0 on end # Slot3 173 device pci a.0 on end # Slot2 174 device pci b.0 on end # Slot1 175 device pci c.0 on end # IT8888 176 device pci e.0 on end # Ethernet 177 device pci f.0 on # ISA bridge 178 chip superio/ite/it8712f 179 device pnp 2e.0 off # Floppy 180 io 0x60 = 0x3f0 181 irq 0x70 = 6 182 drq 0x74 = 2 183 end 184 device pnp 2e.1 on # Com1 185 io 0x60 = 0x3f8 186 irq 0x70 = 4 187 end 188 device pnp 2e.2 on # Com2 189 io 0x60 = 0x2f8 190 irq 0x70 = 3 191 end 192 device pnp 2e.3 on # Parallel port 193 io 0x60 = 0x378 194 irq 0x70 = 7 195 end 196 device pnp 2e.4 on # EC 197 io 0x60 = 0x290 198 io 0x62 = 0x230 199 irq 0x70 = 9 200 end 201 device pnp 2e.5 on # PS/2 keyboard 202 io 0x60 = 0x60 203 io 0x62 = 0x64 204 irq 0x70 = 1 205 end 206 device pnp 2e.6 on # PS/2 mouse 207 irq 0x70 = 12 208 end 209 device pnp 2e.7 on # GPIO 210 io 0x62 = 0x1220 211 # io 0x64 = 0x1200 212 end 213 device pnp 2e.8 off # MIDI 214 io 0x60 = 0x300 215 irq 0x70 = 9 216 end 217 device pnp 2e.9 off # Game port 218 io 0x60 = 0x220 219 end 220 device pnp 2e.a off end # CIR 221 end 222 end 223 device pci f.2 on end # IDE controller 224 device pci f.3 on end # Audio 225 device pci f.4 on end # OHCI 226 device pci f.5 on end # EHCI 227 end 228 end 229 # APIC cluster is late CPU init. 230 device apic_cluster 0 on 231 chip cpu/amd/model_lx 232 device apic 0 on end 233 end 234 end 235 end -
trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb
r3760 r3761 3 3 ## 4 4 ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH 5 ##6 ## Based on Options.lb from AMD's DB800 mainboard.7 5 ## 8 6 ## This program is free software; you can redistribute it and/or modify … … 20 18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 19 ## 20 21 ## Based on Options.lb from AMD's DB800 mainboard. 22 22 23 23 uses HAVE_MP_TABLE … … 81 81 82 82 ## ROM_SIZE is the size of boot ROM that this board will use. 83 default ROM_SIZE = 512*102483 default ROM_SIZE = 512 * 1024 84 84 85 85 ### 86 86 ### Build options 87 87 ### 88 default CONFIG_CONSOLE_VGA =089 default CONFIG_VIDEO_MB =890 default CONFIG_PCI_ROM_RUN =088 default CONFIG_CONSOLE_VGA = 0 89 default CONFIG_VIDEO_MB = 8 90 default CONFIG_PCI_ROM_RUN = 0 91 91 92 92 ## 93 93 ## Build code for the fallback boot 94 94 ## 95 default HAVE_FALLBACK_BOOT =195 default HAVE_FALLBACK_BOOT = 1 96 96 97 97 ## 98 98 ## no MP table 99 99 ## 100 default HAVE_MP_TABLE =0100 default HAVE_MP_TABLE = 0 101 101 102 102 ## 103 103 ## Build code to reset the motherboard from coreboot 104 104 ## 105 default HAVE_HARD_RESET =0105 default HAVE_HARD_RESET = 0 106 106 107 107 ## Delay timer options 108 108 ## 109 default CONFIG_UDELAY_TSC =1110 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 =1109 default CONFIG_UDELAY_TSC = 1 110 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 111 111 112 112 ## 113 113 ## Build code to export a programmable irq routing table 114 114 ## 115 default HAVE_PIRQ_TABLE =1116 default IRQ_SLOT_COUNT =7117 default PIRQ_ROUTE =1115 default HAVE_PIRQ_TABLE = 1 116 default IRQ_SLOT_COUNT = 7 117 default PIRQ_ROUTE = 1 118 118 119 119 ## 120 120 ## Build code to export a CMOS option table 121 121 ## 122 default HAVE_OPTION_TABLE =0122 default HAVE_OPTION_TABLE = 0 123 123 124 124 ### … … 127 127 128 128 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. 129 default ROM_IMAGE_SIZE = 6 5536130 default FALLBACK_SIZE = 1 31072129 default ROM_IMAGE_SIZE = 64 * 1024 130 default FALLBACK_SIZE = 128 * 1024 131 131 132 132 ## 133 133 ## enable CACHE_AS_RAM specifics 134 134 ## 135 default USE_DCACHE_RAM =1136 default DCACHE_RAM_BASE =0xc8000137 default DCACHE_RAM_SIZE =0x08000135 default USE_DCACHE_RAM = 1 136 default DCACHE_RAM_BASE = 0xc8000 137 default DCACHE_RAM_SIZE = 0x08000 138 138 139 139 ## 140 140 ## Use a small 8K stack 141 141 ## 142 default STACK_SIZE =0x2000142 default STACK_SIZE = 8 * 1024 143 143 144 144 ## 145 145 ## Use a small 16K heap 146 146 ## 147 default HEAP_SIZE =0x4000147 default HEAP_SIZE = 16 * 1024 148 148 149 149 ## … … 160 160 ## The default compiler 161 161 ## 162 default CROSS_COMPILE =""163 default CC ="$(CROSS_COMPILE)gcc -m32"164 default HOSTCC ="gcc"162 default CROSS_COMPILE = "" 163 default CC = "$(CROSS_COMPILE)gcc -m32" 164 default HOSTCC = "gcc" 165 165 166 166 ## … … 169 169 170 170 # To Enable the Serial Console 171 default CONFIG_CONSOLE_SERIAL8250 =1171 default CONFIG_CONSOLE_SERIAL8250 = 1 172 172 173 173 ## Select the serial console baud rate 174 default TTYS0_BAUD =115200175 #default TTYS0_BAUD =57600176 #default TTYS0_BAUD =38400177 #default TTYS0_BAUD =19200178 #default TTYS0_BAUD =9600179 #default TTYS0_BAUD =4800180 #default TTYS0_BAUD =2400181 #default TTYS0_BAUD =1200174 default TTYS0_BAUD = 115200 175 #default TTYS0_BAUD = 57600 176 #default TTYS0_BAUD = 38400 177 #default TTYS0_BAUD = 19200 178 #default TTYS0_BAUD = 9600 179 #default TTYS0_BAUD = 4800 180 #default TTYS0_BAUD = 2400 181 #default TTYS0_BAUD = 1200 182 182 183 183 # Select the serial console base port 184 default TTYS0_BASE =0x3f8184 default TTYS0_BASE = 0x3f8 185 185 186 186 # Select the serial protocol 187 187 # This defaults to 8 data bits, 1 stop bit, and no parity 188 default TTYS0_LCS =0x3188 default TTYS0_LCS = 0x3 189 189 190 190 # Compile extra debugging code 191 default DEBUG =1191 default DEBUG = 1 192 192 193 193 ## … … 205 205 206 206 ## Request this level of debugging output 207 default DEFAULT_CONSOLE_LOGLEVEL =8207 default DEFAULT_CONSOLE_LOGLEVEL = 8 208 208 ## At a maximum only compile in this level of debugging 209 default MAXIMUM_CONSOLE_LOGLEVEL =8209 default MAXIMUM_CONSOLE_LOGLEVEL = 8 210 210 211 211 end -
trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
r3760 r3761 4 4 * Copyright (C) 2008 LiPPERT Embedded Computers GmbH 5 5 * Copyright (C) 2007 Advanced Micro Devices, Inc. 6 *7 * Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards.8 6 * 9 7 * This program is free software; you can redistribute it and/or modify … … 21 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 20 */ 21 22 /* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */ 23 23 24 24 #define ASSEMBLY 1 … … 53 53 static inline int spd_read_byte(unsigned int device, unsigned int address) 54 54 { 55 if (device != DIMM0) return 0xFF; // no DIMM1, don't even try 55 if (device != DIMM0) 56 return 0xFF; /* No DIMM1, don't even try. */ 57 56 58 return smbus_read_byte(device, address); 57 59 } … … 121 123 int i; 122 124 123 /* Init Super IO WDT, GPIOs. Done early, WDT init may trigger reset! */125 /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ 124 126 it8712f_enter_conf(); 125 for (i =0; i<ARRAY_SIZE(sio_init_table); i++) {127 for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { 126 128 u16 val = sio_init_table[i]; 127 outb((u8)val, SIO_INDEX); outb(val>>8, SIO_DATA); 129 outb((u8)val, SIO_INDEX); 130 outb(val >> 8, SIO_DATA); 128 131 } 129 132 it8712f_exit_conf(); … … 143 146 cs5536_early_setup(); 144 147 145 /* Note: must do this AFTER the early_setup! It is counting on some 148 /* 149 * Note: must do this AFTER the early_setup! It is counting on some 146 150 * early MSR setup for CS5536. 147 151 */ 148 it8712f_enable_serial(0, TTYS0_BASE); // does not use its 1st parameter152 it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter 149 153 mb_gpio_init(); 150 154 uart_init(); -
trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/chip.h
r3760 r3761 3 3 * 4 4 * Copyright (C) 2008 LiPPERT Embedded Computers GmbH 5 *6 * Based on chip.h from AMD's DB800 mainboard.7 5 * 8 6 * This program is free software; you can redistribute it and/or modify … … 21 19 */ 22 20 21 /* Based on chip.h from AMD's DB800 mainboard. */ 22 23 23 #include <stdint.h> 24 24 … … 26 26 27 27 struct mainboard_lippert_roadrunner_lx_config { 28 u8 sio_gp1x_config; // bit5=Live LED, bit2=RS485_EN2, bit1=RS485_EN1 28 /* bit5 = Live LED, bit2 = RS485_EN2, bit1 = RS485_EN1 */ 29 u8 sio_gp1x_config; 29 30 }; -
trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/irq_tables.c
r3760 r3761 3 3 * 4 4 * Copyright (C) 2008 LiPPERT Embedded Computers GmbH 5 *6 * Based on irq_tables.c from AMD's DB800 mainboard.7 5 * 8 6 * This program is free software; you can redistribute it and/or modify … … 20 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 19 */ 20 21 /* Based on irq_tables.c from AMD's DB800 mainboard. */ 22 22 23 23 #include <arch/pirq_routing.h> … … 48 48 PIRQ_SIGNATURE, /* u32 signature */ 49 49 PIRQ_VERSION, /* u16 version */ 50 32 + 16 * IRQ_SLOT_COUNT, 50 32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */ 51 51 0x00, /* Where the interrupt router lies (bus) */ 52 52 (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ … … 56 56 0, /* Crap (miniport) */ 57 57 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 58 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */58 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 59 59 { 60 61 62 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu*/63 64 65 66 67 68 60 /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ 61 /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ 62 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ 63 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ 64 {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ 65 {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ 66 {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ 67 {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ 68 {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ 69 69 } 70 70 }; -
trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/mainboard.c
r3760 r3761 3 3 * 4 4 * Copyright (C) 2008 LiPPERT Embedded Computers GmbH 5 *6 * Based on mainboard.c from AMD's DB800 mainboard.7 5 * 8 6 * This program is free software; you can redistribute it and/or modify … …