Changeset 3759

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Timestamp:
11/18/08 13:02:03 (7 weeks ago)
Author:
uwe
Message:

i810: Add some more comments, and especially add a list of tested BUFF_SC
values for different DIMM configurations. This should be converted to a
table or code later on and actually be used for BUFF_SC.

Many thanks to Elia Yehuda <z4ziggy@…> for testing and collecting
the table entries.

Signed-off-by: Uwe Hermann <uwe@…>
Acked-by: Uwe Hermann <uwe@…>

Location:
trunk/coreboot-v2/src/northbridge/intel/i82810
Files:
2 modified

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Unmodified
Added
Removed

  • trunk/coreboot-v2/src/northbridge/intel/i82810/i82810.h

    r3052 r3759  
    3131 * PCI Configuration Registers. 
    3232 * 
    33  * Any addresses between 0x00 and 0xff not listed below are reserved and 
     33 * Any addresses between 0x50 and 0xff not listed below are reserved and 
    3434 * should not be touched. 
    3535 */ 
    3636 
    37 /* TODO: Descriptions. */ 
    38 #define GMCHCFG 0x50 
    39 #define PAM     0x51 
    40 #define DRP     0x52 
    41 #define DRAMT   0x53 
    42 #define FDHC    0x58 
     37#define GMCHCFG 0x50            /* GMCH Configuration */ 
     38#define PAM     0x51            /* Programmable Attributes */ 
     39#define DRP     0x52            /* DRAM Row Population */ 
     40#define DRAMT   0x53            /* DRAM Timing */ 
     41#define FDHC    0x58            /* Fixed DRAM Hole Control */ 
    4342#define SMRAM   0x70            /* System Management RAM Control */ 
    44 #define MISSC   0x72 
    45 #define MISSC2  0x80 
    46 #define BUFF_SC 0x92 
     43#define MISSC   0x72            /* Miscellaneous Control */ 
     44#define MISSC2  0x80            /* Miscellaneous Control 2 */ 
     45#define BUFF_SC 0x92            /* System Memory Buffer Strength Control */ 

  • trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c

    r3052 r3759  
    4848 
    4949/* DRAMT[7:5] - SDRAM Mode Select (SMS). */ 
    50 #define RAM_COMMAND_SELF_REFRESH 0x0    /* IE disable refresh */ 
    51 #define RAM_COMMAND_NORMAL       0x1    /* Normal refresh, 15.6us/11.7us for 100/133MHz */ 
    52 #define RAM_COMMAND_NORMAL_FR    0x2    /* Fast refresh, 7.8us/5.85us for 100/133MHz */ 
    53 #define RAM_COMMAND_NOP          0x4 
    54 #define RAM_COMMAND_PRECHARGE    0x5 
    55 #define RAM_COMMAND_MRS          0x6 
    56 #define RAM_COMMAND_CBR          0x7 
     50#define RAM_COMMAND_SELF_REFRESH 0x0 /* Disable refresh */ 
     51#define RAM_COMMAND_NORMAL       0x1 /* Refresh: 15.6/11.7us for 100/133MHz */ 
     52#define RAM_COMMAND_NORMAL_FR    0x2 /* Refresh: 7.8/5.85us for 100/133MHz */ 
     53#define RAM_COMMAND_NOP          0x4 /* NOP command */ 
     54#define RAM_COMMAND_PRECHARGE    0x5 /* All bank precharge */ 
     55#define RAM_COMMAND_MRS          0x6 /* Mode register set */ 
     56#define RAM_COMMAND_CBR          0x7 /* CBR */ 
    5757 
    5858/*----------------------------------------------------------------------------- 
    … …  
    9999-----------------------------------------------------------------------------*/ 
    100100 
     101/* 
     102 * Set DRP - DRAM Row Population Register (Device 0). 
     103 */ 
    101104static void spd_set_dram_size(const struct mem_controller *ctrl, 
    102105                              uint32_t row_offset) 
    … …  
    210213} 
    211214 
     215/* 
     216 * TODO: BUFF_SC needs to be set according to the DRAM tech (x8, x16, 
     217 * or x32), but the datasheet doesn't list all the detaisl. Currently, it 
     218 * needs to be pulled from the output of 'lspci -xxx Rx92'. 
     219 * 
     220 * Common results (tested on actual hardware) are: 
     221 * 
     222 * (DRP: c = 128MB dual sided, d = 128MB single sided, f = 256MB dual sided) 
     223 * 
     224 * BUFF_SC  TOM     DRP    DIMM0                DIMM1 
     225 * ---------------------------------------------------------------------------- 
     226 * 0x3356   128MB   0x0c   128MB dual-sided     - 
     227 * 0xcc56   128MB   0xc0   -                    128MB dual-sided 
     228 * 0x77da   128MB   0x0d   128MB single-sided   - 
     229 * 0xddda   128MB   0xd0   -                    128MB single-sided 
     230 * 0x0001   256MB   0xcc   128MB dual-sided     128MB dual-sided 
     231 * 0x55c6   256MB   0xdd   128MB single-sided   128MB single-sided 
     232 * 0x4445   256MB   0xcd   128MB single-sided   128MB dual-sided 
     233 * 0x1145   256MB   0xdc   128MB dual-sided     128MB single-sided 
     234 * 0x3356   256MB   0x0f   256MB dual-sided     - 
     235 * 0xcc56   256MB   0xf0   -                    256MB dual-sided 
     236 * 0x0001   384MB   0xcf   256MB dual-sided     128MB dual-sided 
     237 * 0x0001   384MB   0xfc   128MB dual-sided     256MB dual-sided 
     238 * 0x1145   384MB   0xdf   256MB dual-sided     128MB single-sided 
     239 * 0x4445   384MB   0xfd   128MB single-sided   256MB dual-sided 
     240 * 0x0001   512MB   0xff   256MB dual-sided     256MB dual-sided 
     241 */ 
    212242static void set_dram_buffer_strength(const struct mem_controller *ctrl) 
    213243{ 
    214         /* TODO: This needs to be set according to the DRAM tech 
    215          * (x8, x16, or x32). Argh, Intel provides no docs on this! 
    216          * Currently, it needs to be pulled from the output of 
    217          * lspci -xxx Rx92 
    218          */ 
    219244        pci_write_config16(ctrl->d0, BUFF_SC, 0x77da); 
    220245}