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Changeset 3638 for trunk/coreboot-v2

Timestamp:

10/06/08 23:00:46 (3 months ago)

Author:

myles

Message:

Whitespace fixes.

Signed-off-by: Myles Watson <mylesgw@…>
Acked-by: Myles Watson <mylesgw@…>

Location:

trunk/coreboot-v2/src/mainboard

Files:

: 30 modified

nvidia/l1_2pvv/Config.lb (modified) (13 diffs)
nvidia/l1_2pvv/Options.lb (modified) (5 diffs)
nvidia/l1_2pvv/apc_auto.c (modified) (6 diffs)
nvidia/l1_2pvv/cache_as_ram_auto.c (modified) (10 diffs)
nvidia/l1_2pvv/cmos.layout (modified) (3 diffs)
nvidia/l1_2pvv/get_bus_conf.c (modified) (7 diffs)
nvidia/l1_2pvv/irq_tables.c (modified) (4 diffs)
nvidia/l1_2pvv/mb_sysconf.h (modified) (1 diff)
nvidia/l1_2pvv/mptable.c (modified) (7 diffs)
nvidia/l1_2pvv/resourcemap.c (modified) (4 diffs)
tyan/s2912/Config.lb (modified) (11 diffs)
tyan/s2912/Options.lb (modified) (5 diffs)
tyan/s2912/apc_auto.c (modified) (5 diffs)
tyan/s2912/cache_as_ram_auto.c (modified) (10 diffs)
tyan/s2912/cmos.layout (modified) (3 diffs)
tyan/s2912/get_bus_conf.c (modified) (4 diffs)
tyan/s2912/irq_tables.c (modified) (4 diffs)
tyan/s2912/mb_sysconf.h (modified) (1 diff)
tyan/s2912/mptable.c (modified) (5 diffs)
tyan/s2912/resourcemap.c (modified) (4 diffs)
tyan/s2912_fam10/Config.lb (modified) (13 diffs)
tyan/s2912_fam10/Options.lb (modified) (5 diffs)
tyan/s2912_fam10/apc_auto.c (modified) (5 diffs)
tyan/s2912_fam10/cache_as_ram_auto.c (modified) (15 diffs)
tyan/s2912_fam10/cmos.layout (modified) (3 diffs)
tyan/s2912_fam10/get_bus_conf.c (modified) (3 diffs)
tyan/s2912_fam10/irq_tables.c (modified) (5 diffs)
tyan/s2912_fam10/mb_sysconf.h (modified) (1 diff)
tyan/s2912_fam10/mptable.c (modified) (5 diffs)
tyan/s2912_fam10/resourcemap.c (modified) (4 diffs)

Legend:

: Unmodified
: Added
: Removed

trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb

r3079	r3638
1		##
	1	##
2	2	## This file is part of the coreboot project.
3		##
	3	##
4	4	## Copyright (C) 2007 AMD
5	5	## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6		##
	6	##
7	7	## This program is free software; you can redistribute it and/or modify
8	8	## it under the terms of the GNU General Public License as published by
9	9	## the Free Software Foundation; either version 2 of the License, or
10	10	## (at your option) any later version.
11		##
	11	##
12	12	## This program is distributed in the hope that it will be useful,
13	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
14	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15	15	## GNU General Public License for more details.
16		##
	16	##
17	17	## You should have received a copy of the GNU General Public License
18	18	## along with this program; if not, write to the Free Software
19	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20		##
	20	##
21	21
22	22	##
…	…
41	41	## The coreboot bootloader.
42	42	##
43		default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
	43	default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
44	44	default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
45	45
…	…
68	68	end
69	69
70		arch i386 end
	70	arch i386 end
71	71
72	72	##
…	…
83	83
84	84	if HAVE_ACPI_TABLES
85		object acpi_tables.o
86		object fadt.o
	85	object acpi_tables.o
	86	object fadt.o
87	87	makerule dsdt.c
88	88	depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
…	…
90	90	action "mv dsdt_lb.hex dsdt.c"
91	91	end
92		object ./dsdt.o
	92	object ./dsdt.o
93	93
94	94	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
95
96		if ACPI_SSDTX_NUM
97		makerule ssdt6.c
98		depends "$(MAINBOARD)/dx/pci6.asl"
99		action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
100		action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
101		action "mv pci6.hex ssdt6.c"
102		end
103		object ./ssdt6.o
104		makerule ssdt5.c
105		depends "$(MAINBOARD)/dx/pci5.asl"
106		action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
107		action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
108		action "mv pci5.hex ssdt5.c"
109		end
110		object ./ssdt5.o
111		end
	95
	96	if ACPI_SSDTX_NUM
	97	makerule ssdt6.c
	98	depends "$(MAINBOARD)/dx/pci6.asl"
	99	action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
	100	action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
	101	action "mv pci6.hex ssdt6.c"
	102	end
	103	object ./ssdt6.o
	104	makerule ssdt5.c
	105	depends "$(MAINBOARD)/dx/pci5.asl"
	106	action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
	107	action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
	108	action "mv pci5.hex ssdt5.c"
	109	end
	110	object ./ssdt5.o
	111	end
112	112	end
113	113
114	114	if USE_DCACHE_RAM
115	115
116		if CONFIG_USE_INIT
	116	if CONFIG_USE_INIT
117	117	makerule ./cache_as_ram_auto.o
118		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
119		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
	118	depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
	119	action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
120	120	end
121	121	else
122	122	makerule ./cache_as_ram_auto.inc
123		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
124		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
125		action "perl -e 's/.rodata/.rom.data/g' -pi $@"
126		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
	123	depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
	124	action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
	125	action "perl -e 's/.rodata/.rom.data/g' -pi $@"
	126	action "perl -e 's/.text/.section .rom.text/g' -pi $@"
127	127	end
128	128	end
…	…
133	133	else
134	134	if CONFIG_AP_CODE_IN_CAR
135		makerule ./apc_auto.o
136		depends "$(MAINBOARD)/apc_auto.c option_table.h"
137		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
138		end
139		ldscript /arch/i386/init/ldscript_apc.lb
	135	makerule ./apc_auto.o
	136	depends "$(MAINBOARD)/apc_auto.c option_table.h"
	137	action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
	138	end
	139	ldscript /arch/i386/init/ldscript_apc.lb
140	140	end
141	141	end
…	…
160	160
161	161	if USE_DCACHE_RAM
162		if CONFIG_USE_INIT
163		ldscript /cpu/x86/32bit/entry32.lds
164		end
165
166		if CONFIG_USE_INIT
167		ldscript /cpu/amd/car/cache_as_ram.lds
168		end
	162	if CONFIG_USE_INIT
	163	ldscript /cpu/x86/32bit/entry32.lds
	164	end
	165
	166	if CONFIG_USE_INIT
	167	ldscript /cpu/amd/car/cache_as_ram.lds
	168	end
169	169	end
170	170
…	…
174	174	##
175	175	if HAVE_FAILOVER_BOOT
176		if USE_FAILOVER_IMAGE
177		mainboardinit cpu/x86/16bit/reset16.inc
178		ldscript /cpu/x86/16bit/reset16.lds
	176	if USE_FAILOVER_IMAGE
	177	mainboardinit cpu/x86/16bit/reset16.inc
	178	ldscript /cpu/x86/16bit/reset16.lds
179	179	else
180		mainboardinit cpu/x86/32bit/reset32.inc
181		ldscript /cpu/x86/32bit/reset32.lds
182		end
183		else
184		if USE_FALLBACK_IMAGE
185		mainboardinit cpu/x86/16bit/reset16.inc
186		ldscript /cpu/x86/16bit/reset16.lds
	180	mainboardinit cpu/x86/32bit/reset32.inc
	181	ldscript /cpu/x86/32bit/reset32.lds
	182	end
	183	else
	184	if USE_FALLBACK_IMAGE
	185	mainboardinit cpu/x86/16bit/reset16.inc
	186	ldscript /cpu/x86/16bit/reset16.lds
187	187	else
188		mainboardinit cpu/x86/32bit/reset32.inc
189		ldscript /cpu/x86/32bit/reset32.lds
	188	mainboardinit cpu/x86/32bit/reset32.inc
	189	ldscript /cpu/x86/32bit/reset32.lds
190	190	end
191	191	end
…	…
201	201	##
202	202	if HAVE_FAILOVER_BOOT
203		if USE_FAILOVER_IMAGE
	203	if USE_FAILOVER_IMAGE
204	204	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
205	205	ldscript /southbridge/nvidia/mcp55/romstrap.lds
206	206	end
207	207	else
208		if USE_FALLBACK_IMAGE
	208	if USE_FALLBACK_IMAGE
209	209	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
210	210	ldscript /southbridge/nvidia/mcp55/romstrap.lds
…	…
220	220
221	221	###
222		### This is the early phase of coreboot startup
	222	### This is the early phase of coreboot startup
223	223	### Things are delicate and we test to see if we should
224	224	### failover to another image.
…	…
251	251
252	252	##
253		## Include the secondary Configuration files
	253	## Include the secondary Configuration files
254	254	##
255	255	if CONFIG_CHIP_NAME
…	…
258	258
259	259	chip northbridge/amd/amdk8/root_complex
260		device apic_cluster 0 on
261		chip cpu/amd/socket_F
262		device apic 0 on end
263		end
264		end
	260	device apic_cluster 0 on
	261	chip cpu/amd/socket_F
	262	device apic 0 on end
	263	end
	264	end
265	265	device pci_domain 0 on
266	266	chip northbridge/amd/amdk8 #mc0
267		device pci 18.0 on
268		# devices on link 0, link 0 == LDT 0
269		~~chip southbridge/nvidia/mcp55~~
	267	device pci 18.0 on
	268	# devices on link 0, link 0 == LDT 0
	269	chip southbridge/nvidia/mcp55
270	270	device pci 0.0 on end # HT
271		device pci 1.0 on # LPC
	271	device pci 1.0 on # LPC
272	272	chip superio/winbond/w83627ehg
273	273	device pnp 2e.0 off # Floppy
274		io 0x60 = 0x3f0
275		irq 0x70 = 6
276		drq 0x74 = 2
277		end
278		device pnp 2e.1 off # Parallel Port
279		io 0x60 = 0x378
280		irq 0x70 = 7
281		end
282		device pnp 2e.2 on # Com1
283		io 0x60 = 0x3f8
284		irq 0x70 = 4
285		end
286		device pnp 2e.3 off # Com2
287		io 0x60 = 0x2f8
288		irq 0x70 = 3
289		end
290		device pnp 2e.5 on # Keyboard
291		io 0x60 = 0x60
292		io 0x62 = 0x64
293		irq 0x70 = 1
	274	io 0x60 = 0x3f0
	275	irq 0x70 = 6
	276	drq 0x74 = 2
	277	end
	278	device pnp 2e.1 off # Parallel Port
	279	io 0x60 = 0x378
	280	irq 0x70 = 7
	281	end
	282	device pnp 2e.2 on # Com1
	283	io 0x60 = 0x3f8
	284	irq 0x70 = 4
	285	end
	286	device pnp 2e.3 off # Com2
	287	io 0x60 = 0x2f8
	288	irq 0x70 = 3
	289	end
	290	device pnp 2e.5 on # Keyboard
	291	io 0x60 = 0x60
	292	io 0x62 = 0x64
	293	irq 0x70 = 1
294	294	irq 0x72 = 12
295	295	end
296		device pnp 2e.6 off # SFI
297		io 0x62 = 0x100
298		end
299		device pnp 2e.7 off # GPIO_GAME_MIDI
	296	device pnp 2e.6 off # SFI
	297	io 0x62 = 0x100
	298	end
	299	device pnp 2e.7 off # GPIO_GAME_MIDI
300	300	io 0x60 = 0x220
301	301	io 0x62 = 0x300
302	302	irq 0x70 = 9
303		end
304		device pnp 2e.8 off end # WDTO_PLED
305		device pnp 2e.9 off end # GPIO_SUSLED
306		device pnp 2e.a off end # ACPI
307		device pnp 2e.b on # HW Monitor
	303	end
	304	device pnp 2e.8 off end # WDTO_PLED
	305	device pnp 2e.9 off end # GPIO_SUSLED
	306	device pnp 2e.a off end # ACPI
	307	device pnp 2e.b on # HW Monitor
308	308	io 0x60 = 0x290
309	309	irq 0x70 = 5
310		end
	310	end
311	311	end
312	312	end
313		device pci 1.1 on # SM 0
314		chip drivers/generic/generic #dimm 0-0-0
315		device i2c 50 on end
316		end
317		chip drivers/generic/generic #dimm 0-0-1
318		device i2c 51 on end
319		end
320		chip drivers/generic/generic #dimm 0-1-0
321		device i2c 52 on end
322		end
323		chip drivers/generic/generic #dimm 0-1-1
324		device i2c 53 on end
325		end
326		chip drivers/generic/generic #dimm 1-0-0
327		device i2c 54 on end
328		end
329		chip drivers/generic/generic #dimm 1-0-1
330		device i2c 55 on end
331		end
332		chip drivers/generic/generic #dimm 1-1-0
333		device i2c 56 on end
334		end
335		chip drivers/generic/generic #dimm 1-1-1
336		device i2c 57 on end
337		end
	313	device pci 1.1 on # SM 0
	314	chip drivers/generic/generic #dimm 0-0-0
	315	device i2c 50 on end
	316	end
	317	chip drivers/generic/generic #dimm 0-0-1
	318	device i2c 51 on end
	319	end
	320	chip drivers/generic/generic #dimm 0-1-0
	321	device i2c 52 on end
	322	end
	323	chip drivers/generic/generic #dimm 0-1-1
	324	device i2c 53 on end
	325	end
	326	chip drivers/generic/generic #dimm 1-0-0
	327	device i2c 54 on end
	328	end
	329	chip drivers/generic/generic #dimm 1-0-1
	330	device i2c 55 on end
	331	end
	332	chip drivers/generic/generic #dimm 1-1-0
	333	device i2c 56 on end
	334	end
	335	chip drivers/generic/generic #dimm 1-1-1
	336	device i2c 57 on end
	337	end
338	338	end # SM
339		device pci 1.1 on # SM 1
	339	device pci 1.1 on # SM 1
340	340	#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
341		# chip drivers/generic/generic #PCIXA Slot1
342		# device i2c 50 on end
343		# end
344		# chip drivers/generic/generic #PCIXB Slot1
345		# device i2c 51 on end
346		# ~~end~~
347		# chip drivers/generic/generic #PCIXB Slot2
348		# device i2c 52 on end
349		# ~~end~~
350		# chip drivers/generic/generic #PCI Slot1
351		# device i2c 53 on end
352		# ~~end~~
353		# chip drivers/generic/generic #Master MCP55 PCI-E
354		# device i2c 54 on end
355		# ~~end~~
356		# chip drivers/generic/generic #Slave MCP55 PCI-E
357		# device i2c 55 on end
358		# ~~end~~
359		chip drivers/generic/generic #MAC EEPROM
360		device i2c 51 on end
361		end
362
363		end # SM
364		device pci 2.0 on end # USB 1.1
365		device pci 2.1 on end # USB 2
366		device pci 4.0 on end # IDE
367		device pci 5.0 on end # SATA 0
368		device pci 5.1 on end # SATA 1
369		device pci 5.2 on end # SATA 2
370		device pci 6.0 on end # PCI
371		device pci 6.1 on end # AZA
372		device pci 8.0 on end # NIC
373		device pci 9.0 on end # NIC
374		device pci a.0 on end # PCI E 5
375		device pci b.0 off end # PCI E 4
376		device pci c.0 off end # PCI E 3
377		device pci d.0 on end # PCI E 2
378		device pci e.0 off end # PCI E 1
379		device pci f.0 on end # PCI E 0
380		register "ide0_enable" = "1"
381		register "sata0_enable" = "1"
382		register "sata1_enable" = "1"
	341	# chip drivers/generic/generic #PCIXA Slot1
	342	# device i2c 50 on end
	343	# end
	344	# chip drivers/generic/generic #PCIXB Slot1
	345	# device i2c 51 on end
	346	# end
	347	# chip drivers/generic/generic #PCIXB Slot2
	348	# device i2c 52 on end
	349	# end
	350	# chip drivers/generic/generic #PCI Slot1
	351	# device i2c 53 on end
	352	# end
	353	# chip drivers/generic/generic #Master MCP55 PCI-E
	354	# device i2c 54 on end
	355	# end
	356	# chip drivers/generic/generic #Slave MCP55 PCI-E
	357	# device i2c 55 on end