Changeset 3633
- Timestamp:
- 10/02/08 21:21:30 (3 months ago)
- Location:
- trunk/coreboot-v2/src/superio
- Files:
-
- 7 modified
-
smsc/lpc47b397/lpc47b397.h (modified) (1 diff)
-
smsc/lpc47b397/lpc47b397_early_gpio.c (modified) (2 diffs)
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smsc/lpc47b397/lpc47b397_early_serial.c (modified) (1 diff)
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smsc/lpc47b397/superio.c (modified) (9 diffs)
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winbond/w83627hf/superio.c (modified) (11 diffs)
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winbond/w83627hf/w83627hf.h (modified) (2 diffs)
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winbond/w83627hf/w83627hf_early_serial.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h
r1946 r3633 1 #define LPC47B397_FDC 0/* Floppy */2 #define LPC47B397_PP 3/* Parallel Port */3 #define LPC47B397_SP1 4/* Com1 */4 #define LPC47B397_SP2 5/* Com2 */5 #define LPC47B397_KBC 7/* Keyboard & Mouse */6 #define LPC47B397_HWM 8/* HW Monitor */7 #define LPC47B397_RT 10/* Runtime reg*/1 #define LPC47B397_FDC 0 /* Floppy */ 2 #define LPC47B397_PP 3 /* Parallel Port */ 3 #define LPC47B397_SP1 4 /* Com1 */ 4 #define LPC47B397_SP2 5 /* Com2 */ 5 #define LPC47B397_KBC 7 /* Keyboard & Mouse */ 6 #define LPC47B397_HWM 8 /* HW Monitor */ 7 #define LPC47B397_RT 10 /* Runtime reg*/ -
trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
r1946 r3633 3 3 outb(value,iobase+offset); 4 4 } 5 5 6 static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) 6 7 { 7 8 return inb(iobase+offset); 8 9 } 9 10 … … 14 15 static void lpc47b397_gpio_index_out(unsigned iobase, unsigned index, unsigned value) 15 16 { 16 17 outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); 17 18 outb(value, iobase+LPC47B397_GPIO_CNTL_DATA); 18 19 } 20 19 21 static unsigned lpc47b397_gpio_index_in(unsigned iobase, unsigned index) 20 22 { 21 23 outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); 22 24 return inb(iobase+LPC47B397_GPIO_CNTL_DATA); 23 25 } 24 26 25 -
trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
r1946 r3633 4 4 static inline void pnp_enter_conf_state(device_t dev) { 5 5 unsigned port = dev>>8; 6 6 outb(0x55, port); 7 7 } 8 8 9 static void pnp_exit_conf_state(device_t dev) { 9 10 unsigned port = dev>>8; 10 11 outb(0xaa, port); 11 12 } 13 12 14 static void lpc47b397_enable_serial(device_t dev, unsigned iobase) 13 15 { -
trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c
r3624 r3633 1 1 /* Copyright 2000 AG Electronics Ltd. */ 2 2 /* Copyright 2003-2004 Linux Networx */ 3 /* Copyright 2004 Tyan 4 */ 3 /* Copyright 2004 Tyan 4 */ 5 5 6 6 /* This code is distributed without warranty under the GPL v2 (see COPYING) */ … … 21 21 22 22 static void pnp_enter_conf_state(device_t dev) { 23 23 outb(0x55, dev->path.u.pnp.port); 24 24 } 25 25 static void pnp_exit_conf_state(device_t dev) { 26 26 outb(0xaa, dev->path.u.pnp.port); 27 27 } 28 28 29 29 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value) 30 30 { 31 32 31 outb(reg, port_base); 32 outb(value, port_base + 1); 33 33 } 34 34 35 35 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg) 36 36 { 37 38 37 outb(reg, port_base); 38 return inb(port_base + 1); 39 39 } 40 40 41 41 static void enable_hwm_smbus(device_t dev) { 42 42 /* enable SensorBus register access */ 43 44 reg = 0xf0; 45 46 47 48 } 43 uint8_t reg, value; 44 reg = 0xf0; 45 value = pnp_read_config(dev, reg); 46 value |= 0x01; 47 pnp_write_config(dev, reg, value); 48 } 49 49 50 50 … … 58 58 conf = dev->chip_info; 59 59 switch(dev->path.u.pnp.device) { 60 case LPC47B397_SP1: 60 case LPC47B397_SP1: 61 61 res0 = find_resource(dev, PNP_IDX_IO0); 62 62 init_uart8250(res0->base, &conf->com1); … … 72 72 break; 73 73 } 74 74 75 75 } 76 76 … … 78 78 { 79 79 80 pnp_enter_conf_state(dev); 80 pnp_enter_conf_state(dev); 81 81 82 82 pnp_set_resources(dev); 83 83 84 84 #if 0 85 85 dump_pnp_device(dev); 86 86 #endif 87 88 pnp_exit_conf_state(dev); 89 90 } 91 87 88 pnp_exit_conf_state(dev); 89 90 } 91 92 92 void lpc47b397_pnp_enable_resources(device_t dev) 93 { 94 95 96 97 98 99 100 101 93 { 94 95 pnp_enter_conf_state(dev); 96 97 pnp_enable_resources(dev); 98 99 switch(dev->path.u.pnp.device) { 100 case LPC47B397_HWM: 101 printk_debug("lpc47b397 SensorBus Register Access enabled\r\n"); 102 102 pnp_set_logical_device(dev); 103 104 105 106 107 #if 0 108 103 enable_hwm_smbus(dev); 104 break; 105 } 106 107 #if 0 108 dump_pnp_device(dev); 109 109 #endif 110 110 111 111 pnp_exit_conf_state(dev); 112 112 113 113 } … … 116 116 { 117 117 118 pnp_enter_conf_state(dev); 118 pnp_enter_conf_state(dev); 119 119 120 120 pnp_set_logical_device(dev); … … 127 127 } 128 128 129 pnp_exit_conf_state(dev); 130 129 pnp_exit_conf_state(dev); 130 131 131 } 132 132 … … 150 150 static int lsmbus_read_byte(device_t dev, uint8_t address) 151 151 { 152 153 152 unsigned device; 153 struct resource *res; 154 154 int result; 155 155 156 157 158 156 device = dev->path.u.i2c.device; 157 158 res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); 159 159 160 160 pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0? 161 161 162 162 result = pnp_read_index(res->base+SB_INDEX, address); // we only read it one byte one time 163 164 163 164 return result; 165 165 } 166 166 167 167 static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) 168 { 169 170 171 172 168 { 169 unsigned device; 170 struct resource *res; 171 172 device = dev->path.u.i2c.device; 173 173 res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); 174 174 175 176 177 178 179 175 pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0? 176 177 pnp_write_index(res->base+SB_INDEX, address, val); // we only write it one byte one time 178 179 return 0; 180 180 } 181 181 182 182 static struct smbus_bus_operations lops_smbus_bus = { 183 // 184 // 185 186 183 // .recv_byte = lsmbus_recv_byte, 184 // .send_byte = lsmbus_send_byte, 185 .read_byte = lsmbus_read_byte, 186 .write_byte = lsmbus_write_byte, 187 187 }; 188 188 static struct device_operations ops_hwm = { 189 190 191 192 193 189 .read_resources = pnp_read_resources, 190 .set_resources = lpc47b397_pnp_set_resources, 191 .enable_resources = lpc47b397_pnp_enable_resources, 192 .enable = lpc47b397_pnp_enable, 193 .init = lpc47b397_init, 194 194 .scan_bus = scan_static_bus, 195 195 .ops_smbus_bus = &lops_smbus_bus, … … 197 197 198 198 static struct pnp_info pnp_dev_info[] = { 199 200 201 202 203 199 { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, 200 { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, 201 { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, 202 { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, 203 { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, 204 204 { &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, }, 205 205 { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, }, 206 206 }; 207 207 -
trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c
r3624 r3633 1 1 /* Copyright 2000 AG Electronics Ltd. */ 2 2 /* Copyright 2003-2004 Linux Networx */ 3 /* Copyright 2004 Tyan 3 /* Copyright 2004 Tyan 4 4 By LYH change from PC87360 */ 5 5 /* This code is distributed without warranty under the GPL v2 (see COPYING) */ … … 19 19 20 20 21 static void pnp_enter_ext_func_mode(device_t dev) 21 static void pnp_enter_ext_func_mode(device_t dev) 22 22 { 23 24 23 outb(0x87, dev->path.u.pnp.port); 24 outb(0x87, dev->path.u.pnp.port); 25 25 } 26 static void pnp_exit_ext_func_mode(device_t dev) 26 static void pnp_exit_ext_func_mode(device_t dev) 27 27 { 28 28 outb(0xaa, dev->path.u.pnp.port); 29 29 } 30 30 31 31 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value) 32 32 { 33 34 33 outb(reg, port_base); 34 outb(value, port_base + 1); 35 35 } 36 36 37 37 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg) 38 38 { 39 40 41 } 39 outb(reg, port_base); 40 return inb(port_base + 1); 41 } 42 42 43 43 static void enable_hwm_smbus(device_t dev) { … … 57 57 get_option(&power_on, "power_on_after_fail"); 58 58 pnp_enter_ext_func_mode(dev); 59 pnp_write_index(dev->path.u.pnp.port,7,0x0a); 59 pnp_write_index(dev->path.u.pnp.port,7,0x0a); 60 60 value = pnp_read_config(dev, 0xE4); 61 61 value &= ~(3<<5); … … 64 64 } 65 65 pnp_write_config(dev, 0xE4, value); 66 pnp_exit_ext_func_mode(dev); 66 pnp_exit_ext_func_mode(dev); 67 67 } 68 68 … … 73 73 74 74 unsigned hwm_reg_values[] = { 75 /* 76 77 78 79 0x4e, 0x80, 0x00, 80 81 82 83 84 75 /* reg mask data */ 76 0x40, 0xff, 0x81, /* start HWM */ 77 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */ 78 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */ 79 0x4e, 0x80, 0x00, 80 0x43, 0x00, 0xff, 81 0x44, 0x00, 0x3f, 82 0x4c, 0xbf, 0x18, 83 0x4d, 0xff, 0x80 /* turn off beep */ 84 85 85 }; 86 86 … … 106 106 conf = dev->chip_info; 107 107 switch(dev->path.u.pnp.device) { 108 case W83627HF_SP1: 108 case W83627HF_SP1: 109 109 res0 = find_resource(dev, PNP_IDX_IO0); 110 110 init_uart8250(res0->base, &conf->com1); … … 119 119 init_pc_keyboard(res0->base, res1->base, &conf->keyboard); 120 120 break; 121 122 121 case W83627HF_HWM: 122 res0 = find_resource(dev, PNP_IDX_IO0); 123 123 #define HWM_INDEX_PORT 5 124 125 126 127 128 124 init_hwm(res0->base + HWM_INDEX_PORT); 125 break; 126 case W83627HF_ACPI: 127 init_acpi(dev); 128 break; 129 129 } 130 130 } … … 132 132 void w83627hf_pnp_set_resources(device_t dev) 133 133 { 134 pnp_enter_ext_func_mode(dev); 134 pnp_enter_ext_func_mode(dev); 135 135 pnp_set_resources(dev); 136 pnp_exit_ext_func_mode(dev); 137 138 } 139 136 pnp_exit_ext_func_mode(dev); 137 138 } 139 140 140 void w83627hf_pnp_enable_resources(device_t dev) 141 { 142 pnp_enter_ext_func_mode(dev); 143 pnp_enable_resources(dev); 144 141 { 142 pnp_enter_ext_func_mode(dev); 143 pnp_enable_resources(dev); 144 switch(dev->path.u.pnp.device) { 145 145 case W83627HF_HWM: 146 146 printk_debug("w83627hf hwm smbus enabled\n"); … … 148 148 break; 149 149 } 150 pnp_exit_ext_func_mode(dev); 150 pnp_exit_ext_func_mode(dev); 151 151 152 152 } … … 155 155 { 156 156 157 158 pnp_enter_ext_func_mode(dev); 157 if (!dev->enabled) { 158 pnp_enter_ext_func_mode(dev); 159 159 160 161 160 pnp_set_logical_device(dev); 161 pnp_set_enable(dev, 0); 162 162 163 pnp_exit_ext_func_mode(dev); 164 163 pnp_exit_ext_func_mode(dev); 164 } 165 165 } 166 166 … … 174 174 175 175 static struct pnp_info pnp_dev_info[] = { 176 177 178 179 180 181 182 183 184 185 186 187 176 { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, 177 { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, 178 { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, 179 { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, 180 // No 4 { 0,}, 181 { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, 182 { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, 183 { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, 184 { &ops, W83627HF_GPIO2, }, 185 { &ops, W83627HF_GPIO3, }, 186 { &ops, W83627HF_ACPI, }, 187 { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, 188 188 }; 189 189 -
trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h
r1982 r3633 19 19 #define W83627HF_GPCFG2 0xf3 20 20 #define W83627HF_EXTCFG 0xf4 21 #define W83627HF_IOEXT1A 22 #define W83627HF_IOEXT1B 23 #define W83627HF_IOEXT2A 24 #define W83627HF_IOEXT2B 21 #define W83627HF_IOEXT1A 0xf5 22 #define W83627HF_IOEXT1B 0xf6 23 #define W83627HF_IOEXT2A 0xf7 24 #define W83627HF_IOEXT2B 0xf8 25 25 26 26 #define W83627HF_GPDO_0 0x00 … … 41 41 #define W83627HF_GPDI_5 0x0f 42 42 #define W83627HF_GPDO_6 0x10 43 #define W83627HF_GPDO_7A 44 #define W83627HF_GPDO_7B 45 #define W83627HF_GPDO_7C 46 #define W83627HF_GPDO_7D 47 #define W83627HF_GPDI_7A 48 #define W83627HF_GPDI_7B 49 #define W83627HF_GPDI_7C 50 #define W83627HF_GPDI_7D 43 #define W83627HF_GPDO_7A 0x11 44 #define W83627HF_GPDO_7B 0x12 45 #define W83627HF_GPDO_7C 0x13 46 #define W83627HF_GPDO_7D 0x14 47 #define W83627HF_GPDI_7A 0x15 48 #define W83627HF_GPDI_7B 0x16 49 #define W83627HF_GPDI_7C 0x17 50 #define W83627HF_GPDI_7D 0x18 51 51 52 52 #define W83627HF_XIOCNF 0xf0 53 #define W83627HF_XIOBA1H 54 #define W83627HF_XIOBA1L 53 #define W83627HF_XIOBA1H 0xf1 54 #define W83627HF_XIOBA1L 0xf2 55 55 #define W83627HF_XIOSIZE1 0xf3 56 #define W83627HF_XIOBA2H 57 #define W83627HF_XIOBA2L 56 #define W83627HF_XIOBA2H 0xf4 57 #define W83627HF_XIOBA2L 0xf5 58 58 #define W83627HF_XIOSIZE2 0xf6 59 59 #define W83627HF_XMEMCNF1 0xf7 60 60 #define W83627HF_XMEMCNF2 0xf8 61 #define W83627HF_XMEMBAH 62 #define W83627HF_XMEMBAL 61 #define W83627HF_XMEMBAH 0xf9 62 #define W83627HF_XMEMBAL 0xfa 63 63 #define W83627HF_XMEMSIZE 0xfb 64 64 #define W83627HF_XIRQMAP1 0xfc -
trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c
r1737 r3633 2 2 #include "w83627hf.h" 3 3 4 static inline void pnp_enter_ext_func_mode(device_t dev) 4 static inline void pnp_enter_ext_func_mode(device_t dev) 5 5 { 6 6 unsigned port = dev>>8; 7 8 7 outb(0x87, port); 8 outb(0x87, port); 9 9 } 10 static void pnp_exit_ext_func_mode(device_t dev) 10 11 static void pnp_exit_ext_func_mode(device_t dev) 11 12 { 12 13 unsigned port = dev>>8; 13 14 outb(0xaa, port); 14 15 } 16 15 17 static void w83627hf_enable_serial(device_t dev, unsigned iobase) 16 18 {
