Changeset 3632 for trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h
- Timestamp:
- 10/02/08 21:20:22 (3 months ago)
- Files:
-
- 1 modified
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trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h
r3614 r3632 462 462 463 463 struct dimm_size { 464 uint8_t per_rank; // it is rows + col + bank_lines + data lines */465 uint8_t rows;466 uint8_t col;467 uint8_t bank; //1, 2, 3 mean 2, 4, 8468 uint8_t rank;464 uint8_t per_rank; // it is rows + col + bank_lines + data lines */ 465 uint8_t rows; 466 uint8_t col; 467 uint8_t bank; //1, 2, 3 mean 2, 4, 8 468 uint8_t rank; 469 469 } __attribute__((packed)); 470 470 471 471 struct mem_info { // pernode 472 uint32_t dimm_mask;473 struct dimm_size sz[DIMM_SOCKETS];474 uint32_t x4_mask;475 uint32_t x16_mask;472 uint32_t dimm_mask; 473 struct dimm_size sz[DIMM_SOCKETS]; 474 uint32_t x4_mask; 475 uint32_t x16_mask; 476 476 uint32_t single_rank_mask; 477 uint32_t page_1k_mask;478 // uint32_t ecc_mask;479 // uint32_t registered_mask;480 uint8_t is_opteron;481 uint8_t is_registered;482 uint8_t is_ecc;483 uint8_t is_Width128;477 uint32_t page_1k_mask; 478 // uint32_t ecc_mask; 479 // uint32_t registered_mask; 480 uint8_t is_opteron; 481 uint8_t is_registered; 482 uint8_t is_ecc; 483 uint8_t is_Width128; 484 484 uint8_t is_64MuxMode; 485 uint8_t memclk_set; // we need to use this to retrieve the mem param485 uint8_t memclk_set; // we need to use this to retrieve the mem param 486 486 uint8_t rsv[2]; 487 487 } __attribute__((packed)); 488 488 489 489 struct link_pair_st { 490 device_t udev;491 uint32_t upos;492 uint32_t uoffs;493 device_t dev;494 uint32_t pos;495 uint32_t offs;490 device_t udev; 491 uint32_t upos; 492 uint32_t uoffs; 493 device_t dev; 494 uint32_t pos; 495 uint32_t offs; 496 496 497 497 } __attribute__((packed)); 498 498 499 499 struct sys_info { 500 uint8_t ctrl_present[NODE_NUMS];501 struct mem_info meminfo[NODE_NUMS];500 uint8_t ctrl_present[NODE_NUMS]; 501 struct mem_info meminfo[NODE_NUMS]; 502 502 struct mem_controller ctrl[NODE_NUMS]; 503 503 uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail 504 uint32_t tom_k;505 uint32_t tom2_k;504 uint32_t tom_k; 505 uint32_t tom2_k; 506 506 507 507 uint32_t mem_base[NODE_NUMS]; … … 512 512 uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8 513 513 uint32_t nodes; 514 struct link_pair_st link_pair[16];// enough? only in_conherent515 uint32_t link_pair_num;516 uint32_t ht_c_num;514 struct link_pair_st link_pair[16];// enough? only in_conherent 515 uint32_t link_pair_num; 516 uint32_t ht_c_num; 517 517 uint32_t sbdn; 518 518 uint32_t sblk; … … 527 527 { 528 528 529 int i;530 uint32_t mask = 0;529 int i; 530 uint32_t mask = 0; 531 531 unsigned needs_reset = 0; 532 532 … … 534 534 if(sysinfo->nodes == 1) return; // in case only one cpu installed 535 535 536 for(i=1; i<sysinfo->nodes; i++) {537 /* Skip everything if I don't have any memory on this controller */538 if(sysinfo->mem_trained[i]==0x00) continue;539 540 mask |= (1<<i);541 542 }543 544 i = 1;545 while(1) {536 for(i=1; i<sysinfo->nodes; i++) { 537 /* Skip everything if I don't have any memory on this controller */ 538 if(sysinfo->mem_trained[i]==0x00) continue; 539 540 mask |= (1<<i); 541 542 } 543 544 i = 1; 545 while(1) { 546 546 if(mask & (1<<i)) { 547 547 if((sysinfo->mem_trained[i])!=0x80) { … … 550 550 } 551 551 552 if(!mask) break;552 if(!mask) break; 553 553 554 554 #if 0 … … 557 557 #endif 558 558 559 i++;560 i%=sysinfo->nodes;559 i++; 560 i%=sysinfo->nodes; 561 561 } 562 562 … … 567 567 printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 568 568 #endif 569 switch(sysinfo->mem_trained[i]) {569 switch(sysinfo->mem_trained[i]) { 570 570 case 0: //don't need train 571 571 case 1: //trained
