Changeset 3632
- Timestamp:
- 10/02/08 21:20:22 (7 weeks ago)
- Location:
- trunk/coreboot-v2/src/northbridge/amd/amdk8
- Files:
-
- 18 modified
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Config.lb (modified) (1 diff)
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amdk8_acpi.c (modified) (8 diffs)
-
amdk8_f.h (modified) (7 diffs)
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amdk8_f_pci.c (modified) (4 diffs)
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coherent_ht.c (modified) (78 diffs)
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debug.c (modified) (13 diffs)
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early_ht.c (modified) (6 diffs)
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get_sblk_pci1234.c (modified) (8 diffs)
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incoherent_ht.c (modified) (43 diffs)
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northbridge.c (modified) (45 diffs)
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raminit.c (modified) (50 diffs)
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raminit_f_dqs.c (modified) (90 diffs)
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raminit_test.c (modified) (10 diffs)
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reset_test.c (modified) (1 diff)
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resourcemap.c (modified) (3 diffs)
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setup_resource_map.c (modified) (7 diffs)
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spd_ddr2.h (modified) (4 diffs)
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ssdt.dsl (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/coreboot-v2/src/northbridge/amd/amdk8/Config.lb
r2968 r3632 20 20 if HAVE_ACPI_TABLES 21 21 object amdk8_acpi.o 22 makerule ssdt.c23 depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"24 action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"25 action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"26 action "mv ssdt.hex ssdt.c"27 end28 object ./ssdt.o22 makerule ssdt.c 23 depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" 24 action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl" 25 action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" 26 action "mv ssdt.hex ssdt.c" 27 end 28 object ./ssdt.o 29 29 end 30 30 -
trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c
r2435 r3632 50 50 unsigned long acpi_create_madt_lapics(unsigned long current) 51 51 { 52 device_t cpu;53 int cpu_index = 0;54 55 for(cpu = all_devices; cpu; cpu = cpu->next) {56 if ((cpu->path.type != DEVICE_PATH_APIC) ||57 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))58 {59 continue;60 }61 if (!cpu->enabled) {62 continue;63 }64 current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id);65 cpu_index++;66 67 }68 69 return current;52 device_t cpu; 53 int cpu_index = 0; 54 55 for(cpu = all_devices; cpu; cpu = cpu->next) { 56 if ((cpu->path.type != DEVICE_PATH_APIC) || 57 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) 58 { 59 continue; 60 } 61 if (!cpu->enabled) { 62 continue; 63 } 64 current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id); 65 cpu_index++; 66 67 } 68 69 return current; 70 70 } 71 71 72 72 unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint) 73 73 { 74 device_t cpu; 75 int cpu_index = 0; 76 77 for(cpu = all_devices; cpu; cpu = cpu->next) { 78 if ((cpu->path.type != DEVICE_PATH_APIC) || 79 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) 80 { 81 continue; 82 } 83 if (!cpu->enabled) { 84 continue; 85 } 86 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); 87 cpu_index++; 88 89 } 90 91 return current; 92 } 74 device_t cpu; 75 int cpu_index = 0; 76 77 for(cpu = all_devices; cpu; cpu = cpu->next) { 78 if ((cpu->path.type != DEVICE_PATH_APIC) || 79 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) 80 { 81 continue; 82 } 83 if (!cpu->enabled) { 84 continue; 85 } 86 current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); 87 cpu_index++; 88 89 } 90 91 return current; 92 } 93 93 94 unsigned long acpi_create_srat_lapics(unsigned long current) 94 95 { 95 device_t cpu; 96 int cpu_index = 0; 97 98 for(cpu = all_devices; cpu; cpu = cpu->next) { 99 if ((cpu->path.type != DEVICE_PATH_APIC) || 100 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) 101 { 102 continue; 103 } 104 if (!cpu->enabled) { 105 continue; 106 } 107 printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); 108 current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); 109 cpu_index++; 110 111 } 112 113 return current; 114 } 115 116 96 device_t cpu; 97 int cpu_index = 0; 98 99 for(cpu = all_devices; cpu; cpu = cpu->next) { 100 if ((cpu->path.type != DEVICE_PATH_APIC) || 101 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) 102 { 103 continue; 104 } 105 if (!cpu->enabled) { 106 continue; 107 } 108 printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); 109 current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); 110 cpu_index++; 111 112 } 113 114 return current; 115 } 117 116 118 117 static unsigned long resk(uint64_t value) 119 118 { 120 unsigned long resultk; 121 if (value < (1ULL << 42)) { 122 resultk = value >> 10; 123 } 124 else { 125 resultk = 0xffffffff; 126 } 127 return resultk; 128 } 129 119 unsigned long resultk; 120 if (value < (1ULL << 42)) { 121 resultk = value >> 10; 122 } 123 else { 124 resultk = 0xffffffff; 125 } 126 return resultk; 127 } 130 128 131 129 struct acpi_srat_mem_state { 132 unsigned long current;130 unsigned long current; 133 131 }; 134 132 135 133 void set_srat_mem(void *gp, struct device *dev, struct resource *res) 136 134 { 137 struct acpi_srat_mem_state *state = gp;138 unsigned long basek, sizek;139 basek = resk(res->base);140 sizek = resk(res->size);141 142 printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",143 dev_path(dev), res->index, basek, sizek);144 /*145 0-640K must be on node 0146 next range is from 1M---147 So will cut off before 1M in the mem range148 */149 if((basek+sizek)<1024) return;150 151 if(basek<1024) {152 sizek -= 1024 - basek;153 basek = 1024;154 }155 156 state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV135 struct acpi_srat_mem_state *state = gp; 136 unsigned long basek, sizek; 137 basek = resk(res->base); 138 sizek = resk(res->size); 139 140 printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", 141 dev_path(dev), res->index, basek, sizek); 142 /* 143 0-640K must be on node 0 144 next range is from 1M--- 145 So will cut off before 1M in the mem range 146 */ 147 if((basek+sizek)<1024) return; 148 149 if(basek<1024) { 150 sizek -= 1024 - basek; 151 basek = 1024; 152 } 153 154 state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV 157 155 } 158 156 159 157 unsigned long acpi_fill_srat(unsigned long current) 160 158 { 161 struct acpi_srat_mem_state srat_mem_state;162 163 /* create all subtables for processors */164 current = acpi_create_srat_lapics(current);165 166 /* create all subteble for memory range */167 168 /* 0-640K must be on node 0 */169 current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable170 #if 1 171 srat_mem_state.current = current;172 search_global_resources(173 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,174 set_srat_mem, &srat_mem_state);175 176 current = srat_mem_state.current;177 #endif 178 return current;159 struct acpi_srat_mem_state srat_mem_state; 160 161 /* create all subtables for processors */ 162 current = acpi_create_srat_lapics(current); 163 164 /* create all subteble for memory range */ 165 166 /* 0-640K must be on node 0 */ 167 current += acpi_create_srat_mem((acpi_srat_mem_t *)current, 0, 0, 640, 1);//enable 168 169 srat_mem_state.current = current; 170 search_global_resources( 171 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, 172 set_srat_mem, &srat_mem_state); 173 174 current = srat_mem_state.current; 175 176 return current; 179 177 } 180 178 … … 185 183 /* fill the first 8 byte with that num */ 186 184 /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ 187 185 188 186 /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */ 189 187 static uint8_t hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, … … 193 191 2, 3, 1, 2, 0, 1, 1, 2, 194 192 3, 2, 2, 1, 1, 0, 2, 1, 195 3, 4, 2, 3, 1, 2, 0, 1, 193 3, 4, 2, 3, 1, 2, 0, 1, 196 194 4, 4, 3, 2, 2, 1, 1, 0 }; 197 195 … … 209 207 for(i=0;i<sysconf.hc_possible_num;i++) { 210 208 if((sysconf.pci1234[i]&1) !=1 ) continue; 211 outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node 209 outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node 212 210 } 213 211 #endif 214 212 215 213 for(i=0;i<nodes;i++) { 216 214 for(j=0;j<nodes; j++) { … … 235 233 } 236 234 p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10; 237 #else 235 #else 238 236 p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10; 239 237 #endif … … 244 242 } 245 243 246 current += 8+nodes*nodes;247 248 return current;244 current += 8+nodes*nodes; 245 246 return current; 249 247 } 250 248 … … 256 254 static void int_to_stream(uint32_t val, uint8_t *dest) 257 255 { 258 int i;259 for(i=0;i<4;i++) {260 *(dest+i) = (val >> (8*i)) & 0xff;261 }256 int i; 257 for(i=0;i<4;i++) { 258 *(dest+i) = (val >> (8*i)) & 0xff; 259 } 262 260 } 263 261 … … 267 265 void update_ssdt(void *ssdt) 268 266 { 269 uint8_t *BUSN;270 uint8_t *MMIO;271 uint8_t *PCIO;272 uint8_t *SBLK;273 uint8_t *TOM1;274 uint8_t *SBDN;275 uint8_t *HCLK;276 uint8_t *HCDN;267 uint8_t *BUSN; 268 uint8_t *MMIO; 269 uint8_t *PCIO; 270 uint8_t *SBLK; 271 uint8_t *TOM1; 272 uint8_t *SBDN; 273 uint8_t *HCLK; 274 uint8_t *HCDN; 277 275 uint8_t *CBST; 278 276 279 int i;280 device_t dev;281 uint32_t dword;282 msr_t msr;283 284 BUSN = ssdt+0x3a; //+5 will be next BUSN285 MMIO = ssdt+0x57; //+5 will be next MMIO286 PCIO = ssdt+0xaf; //+5 will be next PCIO287 SBLK = ssdt+0xdc; // one byte288 TOM1 = ssdt+0xe3; //289 SBDN = ssdt+0xed;//290 HCLK = ssdt+0xfa; //+5 will be next HCLK291 HCDN = ssdt+0x12a; //+5 will be next HCDN277 int i; 278 device_t dev; 279 uint32_t dword; 280 msr_t msr; 281 282 BUSN = ssdt+0x3a; //+5 will be next BUSN 283 MMIO = ssdt+0x57; //+5 will be next MMIO 284 PCIO = ssdt+0xaf; //+5 will be next PCIO 285 SBLK = ssdt+0xdc; // one byte 286 TOM1 = ssdt+0xe3; // 287 SBDN = ssdt+0xed; // 288 HCLK = ssdt+0xfa; //+5 will be next HCLK 289 HCDN = ssdt+0x12a; //+5 will be next HCDN 292 290 CBST = ssdt+0x157; // 293 291 294 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));295 for(i=0;i<4;i++) {296 dword = pci_read_config32(dev, 0xe0+i*4);297 int_to_stream(dword, BUSN+i*5);298 }299 for(i=0;i<0x10;i++) {300 dword = pci_read_config32(dev, 0x80+i*4);301 int_to_stream(dword, MMIO+i*5);302 }303 for(i=0;i<0x08;i++) {304 dword = pci_read_config32(dev, 0xc0+i*4);305 int_to_stream(dword, PCIO+i*5);306 }307 308 *SBLK = (uint8_t)(sysconf.sblk);309 310 msr = rdmsr(TOP_MEM);311 int_to_stream(msr.lo, TOM1);312 313 for(i=0;i<sysconf.hc_possible_num;i++) {314 int_to_stream(sysconf.pci1234[i], HCLK + i*5);315 int_to_stream(sysconf.hcdn[i], HCDN + i*5);316 }317 for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8318 int_to_stream(0x00000000, HCLK + i*5);319 int_to_stream(0x20202020, HCDN + i*5);320 }321 322 int_to_stream(sysconf.sbdn, SBDN);292 dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); 293 for(i=0;i<4;i++) { 294 dword = pci_read_config32(dev, 0xe0+i*4); 295 int_to_stream(dword, BUSN+i*5); 296 } 297 for(i=0;i<0x10;i++) { 298 dword = pci_read_config32(dev, 0x80+i*4); 299 int_to_stream(dword, MMIO+i*5); 300 } 301 for(i=0;i<0x08;i++) { 302 dword = pci_read_config32(dev, 0xc0+i*4); 303 int_to_stream(dword, PCIO+i*5); 304 } 305 306 *SBLK = (uint8_t)(sysconf.sblk); 307 308 msr = rdmsr(TOP_MEM); 309 int_to_stream(msr.lo, TOM1); 310 311 for(i=0;i<sysconf.hc_possible_num;i++) { 312 int_to_stream(sysconf.pci1234[i], HCLK + i*5); 313 int_to_stream(sysconf.hcdn[i], HCDN + i*5); 314 } 315 for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8 316 int_to_stream(0x00000000, HCLK + i*5); 317 int_to_stream(0x20202020, HCDN + i*5); 318 } 319 320 int_to_stream(sysconf.sbdn, SBDN); 323 321 324 322 if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 -
trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h
r3614 r3632 462 462 463 463 struct dimm_size { 464 uint8_t per_rank; // it is rows + col + bank_lines + data lines */465 uint8_t rows;466 uint8_t col;467 uint8_t bank; //1, 2, 3 mean 2, 4, 8468 uint8_t rank;464 uint8_t per_rank; // it is rows + col + bank_lines + data lines */ 465 uint8_t rows; 466 uint8_t col; 467 uint8_t bank; //1, 2, 3 mean 2, 4, 8 468 uint8_t rank; 469 469 } __attribute__((packed)); 470 470 471 471 struct mem_info { // pernode 472 uint32_t dimm_mask;473 struct dimm_size sz[DIMM_SOCKETS];474 uint32_t x4_mask;475 uint32_t x16_mask;472 uint32_t dimm_mask; 473 struct dimm_size sz[DIMM_SOCKETS]; 474 uint32_t x4_mask; 475 uint32_t x16_mask; 476 476 uint32_t single_rank_mask; 477 uint32_t page_1k_mask;478 // uint32_t ecc_mask;479 // uint32_t registered_mask;480 uint8_t is_opteron;481 uint8_t is_registered;482 uint8_t is_ecc;483 uint8_t is_Width128;477 uint32_t page_1k_mask; 478 // uint32_t ecc_mask; 479 // uint32_t registered_mask; 480 uint8_t is_opteron; 481 uint8_t is_registered; 482 uint8_t is_ecc; 483 uint8_t is_Width128; 484 484 uint8_t is_64MuxMode; 485 uint8_t memclk_set; // we need to use this to retrieve the mem param485 uint8_t memclk_set; // we need to use this to retrieve the mem param 486 486 uint8_t rsv[2]; 487 487 } __attribute__((packed)); 488 488 489 489 struct link_pair_st { 490 device_t udev;491 uint32_t upos;492 uint32_t uoffs;493 device_t dev;494 uint32_t pos;495 uint32_t offs;490 device_t udev; 491 uint32_t upos; 492 uint32_t uoffs; 493 device_t dev; 494 uint32_t pos; 495 uint32_t offs; 496 496 497 497 } __attribute__((packed)); 498 498 499 499 struct sys_info { 500 uint8_t ctrl_present[NODE_NUMS];501 struct mem_info meminfo[NODE_NUMS];500 uint8_t ctrl_present[NODE_NUMS]; 501 struct mem_info meminfo[NODE_NUMS]; 502 502 struct mem_controller ctrl[NODE_NUMS]; 503 503 uint8_t mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail 504 uint32_t tom_k;505 uint32_t tom2_k;504 uint32_t tom_k; 505 uint32_t tom2_k; 506 506 507 507 uint32_t mem_base[NODE_NUMS]; … … 512 512 uint8_t dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8 513 513 uint32_t nodes; 514 struct link_pair_st link_pair[16];// enough? only in_conherent515 uint32_t link_pair_num;516 uint32_t ht_c_num;514 struct link_pair_st link_pair[16];// enough? only in_conherent 515 uint32_t link_pair_num; 516 uint32_t ht_c_num; 517 517 uint32_t sbdn; 518 518 uint32_t sblk; … … 527 527 { 528 528 529 int i;530 uint32_t mask = 0;529 int i; 530 uint32_t mask = 0; 531 531 unsigned needs_reset = 0; 532 532 … … 534 534 if(sysinfo->nodes == 1) return; // in case only one cpu installed 535 535 536 for(i=1; i<sysinfo->nodes; i++) {537 /* Skip everything if I don't have any memory on this controller */538 if(sysinfo->mem_trained[i]==0x00) continue;539 540 mask |= (1<<i);541 542 }543 544 i = 1;545 while(1) {536 for(i=1; i<sysinfo->nodes; i++) { 537 /* Skip everything if I don't have any memory on this controller */ 538 if(sysinfo->mem_trained[i]==0x00) continue; 539 540 mask |= (1<<i); 541 542 } 543 544 i = 1; 545 while(1) { 546 546 if(mask & (1<<i)) { 547 547 if((sysinfo->mem_trained[i])!=0x80) { … … 550 550 } 551 551 552 if(!mask) break;552 if(!mask) break; 553 553 554 554 #if 0 … … 557 557 #endif 558 558 559 i++;560 i%=sysinfo->nodes;559 i++; 560 i%=sysinfo->nodes; 561 561 } 562 562 … … 567 567 printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 568 568 #endif 569 switch(sysinfo->mem_trained[i]) {569 switch(sysinfo->mem_trained[i]) { 570 570 case 0: //don't need train 571 571 case 1: //trained -
trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f_pci.c
r2435 r3632 5 5 static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index) 6 6 { 7 uint32_t dword;7 uint32_t dword; 8 8 9 pci_write_config32(dev, index_reg, index);9 pci_write_config32(dev, index_reg, index); 10 10 11 dword = pci_read_config32(dev, index_reg+0x4);11 dword = pci_read_config32(dev, index_reg+0x4); 12 12 13 return dword;13 return dword; 14 14 } 15 15 … … 17 17 { 18 18 19 pci_write_config32(dev, index_reg, index);19 pci_write_config32(dev, index_reg, index); 20 20 21 pci_write_config32(dev, index_reg + 0x4, data);21 pci_write_config32(dev, index_reg + 0x4, data); 22 22 23 23 } … … 26 26 { 27 27
