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Changeset 3631 for trunk

Timestamp:

10/02/08 20:19:17 (3 months ago)

Author:

uwe

Message:

CK804 coding-style fixed based on an 'indent' run (trivial).

Signed-off-by: Uwe Hermann <uwe@…>
Acked-by: Uwe Hermann <uwe@…>

Location:

trunk/coreboot-v2/src/southbridge/nvidia/ck804

Files:

: 23 modified

chip.h (modified) (2 diffs)
ck804.c (modified) (4 diffs)
ck804.h (modified) (1 diff)
ck804_ac97.c (modified) (3 diffs)
ck804_early_setup.c (modified) (13 diffs)
ck804_early_setup_car.c (modified) (6 diffs)
ck804_early_setup_ss.h (modified) (2 diffs)
ck804_early_smbus.c (modified) (2 diffs)
ck804_enable_rom.c (modified) (2 diffs)
ck804_ht.c (modified) (3 diffs)
ck804_ide.c (modified) (4 diffs)
ck804_lpc.c (modified) (19 diffs)
ck804_nic.c (modified) (10 diffs)
ck804_pci.c (modified) (7 diffs)
ck804_pcie.c (modified) (4 diffs)
ck804_reset.c (modified) (3 diffs)
ck804_sata.c (modified) (7 diffs)
ck804_smbus.c (modified) (6 diffs)
ck804_smbus.h (modified) (7 diffs)
ck804_usb.c (modified) (4 diffs)
ck804_usb2.c (modified) (3 diffs)
id.inc (modified) (2 diffs)
romstrap.inc (modified) (1 diff)

Legend:

: Unmodified
: Added
: Removed

trunk/coreboot-v2/src/southbridge/nvidia/ck804/chip.h

r2546	r3631
2	2	#define CK804_CHIP_H
3	3
4		struct southbridge_nvidia_ck804_config
5		{
	4	struct southbridge_nvidia_ck804_config {
6	5	unsigned int usb1_hc_reset : 1;
7	6	unsigned int ide0_enable : 1;
…	…
17	16	extern struct chip_operations southbridge_nvidia_ck804_ops;
18	17
19		#endif ~~/* CK804_CHIP_H */~~
	18	#endif

trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c

r3584	r3631
5	5
6	6	#include <console/console.h>
7
8	7	#include <arch/io.h>
9
10	8	#include <device/device.h>
11	9	#include <device/pci.h>
…	…
16	14	static uint32_t final_reg;
17	15
18		static device_t find_lpc_dev( ~~device_t dev, unsigned devfn)~~
	16	static device_t find_lpc_dev(device_t dev, unsigned devfn)
19	17	{
20
21	18	device_t lpc_dev;
22	19
23		lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
	20	lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
	21	if (!lpc_dev)
	22	return lpc_dev;
24	23
25		if ( !lpc_dev ) return lpc_dev;
26
27		if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) \|\| (
28		(lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) &&
29		(lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) &&
30		(lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)) ) {
31		uint32_t id;
32		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
33		if ( (id != (PCI_VENDOR_ID_NVIDIA \| (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) &&
34		(id != (PCI_VENDOR_ID_NVIDIA \| (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) &&
35		(id != (PCI_VENDOR_ID_NVIDIA \| (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16)))
36		) {
37		lpc_dev = 0;
38		}
39		}
	24	if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA)
	25	\|\| ((lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC)
	26	&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO)
	27	&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)))
	28	{
	29	uint32_t id;
	30	id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
	31	if ((id != (PCI_VENDOR_ID_NVIDIA \|
	32	(PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16)))
	33	&& (id != (PCI_VENDOR_ID_NVIDIA \|
	34	(PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16)))
	35	&& (id != (PCI_VENDOR_ID_NVIDIA \|
	36	(PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))))
	37	{
	38	lpc_dev = 0;
	39	}
	40	}
40	41
41	42	return lpc_dev;
…	…
45	46	{
46	47	device_t lpc_dev;
47		unsigned index = 0;
48		unsigned index2 = 0;
	48	unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
49	49	uint32_t reg_old, reg;
50	50	uint8_t byte;
51		~~unsigned deviceid;~~
52		~~unsigned vendorid;~~
53	51
54		struct southbridge_nvidia_ck804_config *conf;
55		conf = dev->chip_info;
	52	struct southbridge_nvidia_ck804_config *conf;
	53	conf = dev->chip_info;
56	54
57		unsigned devfn;
58
59		if(dev->device==0x0000) {
	55	if (dev->device == 0x0000) {
60	56	vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
61		deviceid = (vendorid>>16) & 0xffff;
62		// vendorid &= 0xffff;
	57	deviceid = (vendorid >> 16) & 0xffff;
	58	/* vendorid &= 0xffff; */
63	59	} else {
64		// vendorid = dev->vendor;
	60	/* vendorid = dev->vendor; */
65	61	deviceid = dev->device;
66	62	}
67	63
68	64	devfn = (dev->path.u.pci.devfn) & ~7;
69		switch(deviceid) {
70		case PCI_DEVICE_ID_NVIDIA_CK804_SM:
71		index = 16;
72		break;
73		case PCI_DEVICE_ID_NVIDIA_CK804_USB:
74		~~devfn -= (1<<~~3);
75		index = 8;
76		break;
77		case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
78		~~devfn -= (1<<~~3);
79		index = 20;
80		break;
81		case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
82		~~devfn -= (9<<~~3);
83		index = 10;
84		dev->rom_address = conf->nic_rom_address;
85		break;
86		case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
87		~~devfn -= (9<<~~3);
88		index = 10;
89		dev->rom_address = conf->nic_rom_address;
90		break;
91		case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
92		~~devfn -= (3<<~~3);
93		index = 12;
94		break;
95		case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
96		~~devfn -= (3<<~~3);
97		index = 13;
98		break;
99		case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
100		~~devfn -= (5<<~~3);
101		index = 14;
102		dev->rom_address = conf->raid_rom_address;
103		break;
104		case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
105		~~devfn -= (6<<~~3);
106		index = 22;
107		break;
108		case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
109		~~devfn -= (7<<~~3);
110		index = 18;
111		break;
112		case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
113		~~devfn -= (8<<~~3);
114		index = 15;
115		break;
116		case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
117		~~devfn -= (0xa<<~~3);
118		index2 = 19;
119		break;
120		default:
121		index = 0;
	65	switch (deviceid) {
	66	case PCI_DEVICE_ID_NVIDIA_CK804_SM:
	67	index = 16;
	68	break;
	69	case PCI_DEVICE_ID_NVIDIA_CK804_USB:
	70	devfn -= (1 << 3);
	71	index = 8;
	72	break;
	73	case PCI_DEVICE_ID_NVIDIA_CK804_USB2:
	74	devfn -= (1 << 3);
	75	index = 20;
	76	break;
	77	case PCI_DEVICE_ID_NVIDIA_CK804_NIC:
	78	devfn -= (9 << 3);
	79	index = 10;
	80	dev->rom_address = conf->nic_rom_address;
	81	break;
	82	case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE:
	83	devfn -= (9 << 3);
	84	index = 10;
	85	dev->rom_address = conf->nic_rom_address;
	86	break;
	87	case PCI_DEVICE_ID_NVIDIA_CK804_ACI:
	88	devfn -= (3 << 3);
	89	index = 12;
	90	break;
	91	case PCI_DEVICE_ID_NVIDIA_CK804_MCI:
	92	devfn -= (3 << 3);
	93	index = 13;
	94	break;
	95	case PCI_DEVICE_ID_NVIDIA_CK804_IDE:
	96	devfn -= (5 << 3);
	97	index = 14;
	98	dev->rom_address = conf->raid_rom_address;
	99	break;
	100	case PCI_DEVICE_ID_NVIDIA_CK804_SATA0:
	101	devfn -= (6 << 3);
	102	index = 22;
	103	break;
	104	case PCI_DEVICE_ID_NVIDIA_CK804_SATA1:
	105	devfn -= (7 << 3);
	106	index = 18;
	107	break;
	108	case PCI_DEVICE_ID_NVIDIA_CK804_PCI:
	109	devfn -= (8 << 3);
	110	index = 15;
	111	break;
	112	case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E:
	113	devfn -= (0xa << 3);
	114	index2 = 19;
	115	break;
	116	default:
	117	index = 0;
122	118	}
123	119
124		if~~(index2!=~~0) {
	120	if (index2 != 0) {
125	121	int i;
126		for(i=0;i<4;i++) {
127		lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
128		if(!lpc_dev) continue;
	122	for (i = 0; i < 4; i++) {
	123	lpc_dev = find_lpc_dev(dev, devfn - (i << 3));
	124	if (!lpc_dev)
	125	continue;
129	126	index2 -= i;
130	127	break;
131	128	}
132	129
133		if ( lpc_dev ) {
134		reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
135
136		if (!dev->enabled) {
137		reg \|= (1<<index2);
138		}
139
140		if (reg != reg_old) {
141		pci_write_config32(lpc_dev, 0xe4, reg);
142		}
	130	if (lpc_dev) {
	131	reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
	132	if (!dev->enabled)
	133	reg \|= (1 << index2);
	134	if (reg != reg_old)
	135	pci_write_config32(lpc_dev, 0xe4, reg);
143	136	}
144	137
…	…
147	140	}
148	141
	142	lpc_dev = find_lpc_dev(dev, devfn);
	143	if (!lpc_dev)
	144	return;
149	145
150		lpc_dev = find_lpc_dev(dev, devfn);
	146	if (index == 0) {
	147	final_reg = pci_read_config32(lpc_dev, 0xe8);
	148	final_reg &= ~((1 << 16) \| (1 << 8) \| (1 << 20) \| (1 << 10)
	149	\| (1 << 12) \| (1 << 13) \| (1 << 14) \| (1 << 22)
	150	\| (1 << 18) \| (1 << 15));
	151	pci_write_config32(lpc_dev, 0xe8, final_reg);
151	152
152		if ( !lpc_dev ) return;
	153	reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
	154	reg \|= (1 << 20);
	155	if (reg != reg_old)
	156	pci_write_config32(lpc_dev, 0xe4, reg);
153	157
154		if ( index == 0) {
	158	byte = pci_read_config8(lpc_dev, 0x74);
	159	byte \|= ((1 << 1));
	160	pci_write_config8(dev, 0x74, byte);
155	161
156		final_reg = pci_read_config32(lpc_dev, 0xe8);
157		final_reg &= ~((1<<16)\|(1<<8)\|(1<<20)\|(1<<10)\|(1<<12)\|(1<<13)\|(1<<14)\|(1<<22)\|(1<<18)\|(1<<15));
158		pci_write_config32(lpc_dev, 0xe8, final_reg);
159
160		reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
161		reg \|= (1<<20);
162		if (reg != reg_old) {
163		pci_write_config32(lpc_dev, 0xe4, reg);
164		}
165
166		byte = pci_read_config8(lpc_dev, 0x74);
167		byte \|= ((1<<1));
168		pci_write_config8(dev, 0x74, byte);
169
170		byte = pci_read_config8(lpc_dev, 0xdd);
171		byte \|= ((1<<0)\|(1<<3));
172		pci_write_config8(dev, 0xdd, byte);
	162	byte = pci_read_config8(lpc_dev, 0xdd);
	163	byte \|= ((1 << 0) \| (1 << 3));
	164	pci_write_config8(dev, 0xdd, byte);
173	165
174	166	return;
175
176		}
177
178		~~if (!dev->enabled) {~~
179		~~final_reg \|= (1 << index);~~
180		}
181
182		~~if(index == 10 ) {~~
183		~~reg_old = pci_read_config32(lpc_dev, 0xe8);~~
184		~~if (final_reg != reg_old) {~~
185		~~pci_write_config32(lpc_dev, 0xe8, final_reg);~~
186		}
187
188	167	}
189	168
	169	if (!dev->enabled)
	170	final_reg \|= (1 << index);
	171
	172	if (index == 10) {
	173	reg_old = pci_read_config32(lpc_dev, 0xe8);
	174	if (final_reg != reg_old)
	175	pci_write_config32(lpc_dev, 0xe8, final_reg);
	176	}
190	177	}
191	178

trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.h

r1946	r3631
6	6	void ck804_enable(device_t dev);
7	7
8		#endif ~~/* CK804_H */~~
	8	#endif

trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ac97.c

r2891	r3631
3	3	* by yhlu@tyan.com
4	4	*/
	5
5	6	#include <console/console.h>
6	7	#include <device/device.h>
…	…
12	13	static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
13	14	{
14		pci_write_config32(dev, 0x40,
15		((device & 0xffff) << 16) \| (vendor & 0xffff));
	15	pci_write_config32(dev, 0x40,
	16	((device & 0xffff) << 16) \| (vendor & 0xffff));
16	17	}
17	18
18	19	static struct pci_operations lops_pci = {
19		.set_subsystem = lpci_set_subsystem,
	20	.set_subsystem = lpci_set_subsystem,
20	21	};
21	22
22		static struct device_operations ac97audio_ops = {
	23	static struct device_operations ac97audio_ops = {
23	24	.read_resources = pci_dev_read_resources,
24	25	.set_resources = pci_dev_set_resources,
25	26	.enable_resources = pci_dev_enable_resources,
26		~~// .enable~~ = ck804_enable,
	27	// .enable = ck804_enable,
27	28	.init = 0,
28	29	.scan_bus = 0,
…	…
36	37	};
37	38
38
39		static struct device_operations ac97modem_ops = {
	39	static struct device_operations ac97modem_ops = {
40	40	.read_resources = pci_dev_read_resources,
41	41	.set_resources = pci_dev_set_resources,
42	42	.enable_resources = pci_dev_enable_resources,
43		~~// .enable~~ = ck804_enable,
	43	// .enable = ck804_enable,
44	44	.init = 0,
45	45	.scan_bus = 0,

trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c

r3624	r3631
3	3	* by yhlu@tyan.com
4	4	*/
	5
5	6	static int set_ht_link_ck804(uint8_t ht_c_num)
6	7	{
…	…
10	11	}
11	12
12		static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
	13	static void setup_ss_table(unsigned index, unsigned where, unsigned control,
	14	const unsigned int *register_values, int max)
13	15	{
14	16	int i;
15
16	17	unsigned val;
17	18
…	…
22	23	outl(0, index);
23	24
24		for(i = 0; i < max; i++) {
	25	for (i = 0; i < max; i++) {
25	26	unsigned long reg;
26	27	reg = register_values[i];
…	…
30	31	val \|= 1;
31	32	outl(val, control);
32
33	33	}
34	34
…	…
36	36	#define ANACTRL_REG_POS 0x68
37	37
38
39	38	#define SYSCTRL_IO_BASE 0x6000
40	39	#define SYSCTRL_REG_POS 0x64
41	40
42	41	/*
43		16 1 1 2 :0
44		8 8 2 2 :1
45		8 8 4 :2
46		8 4 4 4 :3
47		16 4 :4
	42	* 16 1 1 2 :0
	43	* 8 8 2 2 :1
	44	* 8 8 4 :2
	45	* 8 4 4 4 :3
	46	* 16 4 :4
48	47	*/
49	48
50	49	#ifndef CK804_PCI_E_X
51		#define CK804_PCI_E_X 4
52		#endif
53
54		#if CK804_NUM > 1
55		#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000)
56		#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000)
57
58		#ifndef CK804B_BUSN
59		#define CK804B_BUSN 0x80
60		#endif
61
62		#ifndef CK804B_PCI_E_X
63		#define CK804B_PCI_E_X 4
64		#endif
	50	#define CK804_PCI_E_X 4
	51	#endif
	52
	53	#if CK804_NUM > 1
	54	#define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000)
	55	#define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000)
	56	#ifndef CK804B_BUSN
	57	#define CK804B_BUSN 0x80
	58	#endif
	59	#ifndef CK804B_PCI_E_X
	60	#define CK804B_PCI_E_X 4
	61	#endif
65	62	#endif
66	63
67	64	#ifndef CK804_USE_NIC
68		#define CK804_USE_NIC 0
	65	#define CK804_USE_NIC 0
69	66	#endif
70	67
71	68	#ifndef CK804_USE_ACI
72		#define CK804_USE_ACI 0
	69	#define CK804_USE_ACI 0
73	70	#endif
74	71
…	…
76	73
77	74	#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
78		#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
	75	#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
79	76	#else
80		#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
	77	#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
81	78	#endif
82	79
83	80	#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
84		#define CK804B_DEVN_BASE 1
	81	#define CK804B_DEVN_BASE 1
85	82	#else
86		#define CK804B_DEVN_BASE CK804_DEVN_BASE
87		#endif
88
	83	#define CK804B_DEVN_BASE CK804_DEVN_BASE
	84	#endif
89	85
90	86	static void ck804_early_set_port(void)
91	87	{
92
93	88	static const unsigned int ctrl_devport_conf[] = {
94	89	PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
…	…
104	99
105	100	setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf));
106
107	101	}
108	102
109	103	static void ck804_early_clear_port(void)
110	104	{
111
112	105	static const unsigned int ctrl_devport_conf_clear[] = {
113	106	PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
…	…
123	116
124	117	setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear));
125
126	118	}
127	119
128	120	static void ck804_early_setup(void)
129	121	{
130
131	122	static const unsigned int ctrl_conf[] = {
132	123
133
134
135		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
136		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
137		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
138		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
139
140
141		#if CK804_NUM > 1
142		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
143		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
144		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
145		#endif
146
147
148
149		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
150		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
151		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
152		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
153		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
154		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
155		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
156		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
157
158
159		#if CK804_NUM > 1
160		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
161		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
162		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
163		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
164		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
165		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
166		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
167		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
168		#endif
169
170
171		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
172		RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
173
174		#if CK804_NUM > 1
175		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
176		RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
177		#endif
178
179
180		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
181		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
182		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
183
184		#if CK804_NUM > 1
185		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
186		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
187		RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
188		#endif
189
190
191		RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
192		&