- Timestamp:
- 09/30/08 17:02:40 (7 weeks ago)
- Location:
- trunk/coreboot-v2
- Files:
-
- 7 modified
-
src/mainboard/asus/a8n_e/Config.lb (modified) (10 diffs)
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src/mainboard/asus/a8n_e/Options.lb (modified) (2 diffs)
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src/mainboard/asus/a8n_e/cache_as_ram_auto.c (modified) (6 diffs)
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src/mainboard/asus/a8n_e/get_bus_conf.c (modified) (7 diffs)
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src/mainboard/asus/a8n_e/irq_tables.c (modified) (13 diffs)
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src/mainboard/asus/a8n_e/mptable.c (modified) (9 diffs)
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targets/asus/a8n_e/Config.lb (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
r3079 r3622 22 22 ## 23 23 24 ##25 ## Compute the location and size of where this firmware image26 ## (coreboot plus bootloader) will live in the boot rom chip.27 ##28 24 if USE_FAILOVER_IMAGE 29 25 default ROM_SECTION_SIZE = FAILOVER_SIZE … … 38 34 end 39 35 end 40 41 ##42 ## Compute the start location and size size of the coreboot bootloader.43 ##44 36 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) 45 37 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) 46 47 ## 48 ## Compute where this copy of coreboot will start in the boot ROM. 49 ## 50 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) 51 52 ## 53 ## Compute a range of ROM that can be cached to speed up coreboot 54 ## execution speed. 55 ## 56 ## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) 57 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE 58 ## 59 default XIP_ROM_SIZE = (64 * 1024) 60 38 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) 39 # XIP_ROM_SIZE must be a power of 2. 40 # XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE. 41 default XIP_ROM_SIZE = 64 * 1024 61 42 if USE_FAILOVER_IMAGE 62 43 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) … … 68 49 end 69 50 end 70 71 51 arch i386 end 72 73 ##74 ## Build the objects we have code for in this directory.75 ##76 77 52 driver mainboard.o 78 79 #dir /drivers/ati/ragexl80 81 53 # Needed by irq_tables and mptable and acpi_tables. 82 54 object get_bus_conf.o 83 84 if HAVE_MP_TABLE 85 object mptable.o 86 end 87 88 if HAVE_PIRQ_TABLE 89 object irq_tables.o 90 end 91 55 if HAVE_MP_TABLE object mptable.o end 56 if HAVE_PIRQ_TABLE object irq_tables.o end 92 57 if USE_DCACHE_RAM 93 58 if CONFIG_USE_INIT … … 105 70 end 106 71 end 107 108 ##109 ## Build our 16 bit and 32 bit coreboot entry code.110 ##111 72 if HAVE_FAILOVER_BOOT 112 73 if USE_FAILOVER_IMAGE … … 120 81 end 121 82 end 122 123 83 mainboardinit cpu/x86/32bit/entry32.inc 124 125 84 if USE_DCACHE_RAM 126 85 if CONFIG_USE_INIT … … 129 88 end 130 89 end 131 132 ##133 ## Build our reset vector (this is where coreboot is entered).134 ##135 90 if HAVE_FAILOVER_BOOT 136 91 if USE_FAILOVER_IMAGE … … 150 105 end 151 106 end 152 153 if USE_DCACHE_RAM 154 else 155 ### Should this be in the northbridge code? 107 if USE_DCACHE_RAM 108 else 156 109 mainboardinit arch/i386/lib/cpu_reset.inc 157 110 end 158 159 ## 160 ## Include an ID string (for safe flashing). 161 ## 111 # Include an ID string (for safe flashing). 162 112 mainboardinit southbridge/nvidia/ck804/id.inc 163 113 ldscript /southbridge/nvidia/ck804/id.lds 164 165 ## 166 ## ROMSTRAP table for CK804 167 ## 114 # ROMSTRAP table for CK804. 168 115 if HAVE_FAILOVER_BOOT 169 116 if USE_FAILOVER_IMAGE … … 177 124 end 178 125 end 179 180 if USE_DCACHE_RAM 181 ## 182 ## Setup Cache-As-Ram 183 ## 126 if USE_DCACHE_RAM 184 127 mainboardinit cpu/amd/car/cache_as_ram.inc 185 128 end 186 187 188 ###189 ### This is the early phase of coreboot startup.190 ### Things are delicate and we test to see if we should191 ### failover to another image.192 ###193 129 if HAVE_FAILOVER_BOOT 194 130 if USE_FAILOVER_IMAGE … … 204 140 end 205 141 end 206 207 ###208 ### O.k. We aren't just an intermediary anymore!209 ###210 211 ##212 ## Setup RAM213 ##214 142 if USE_DCACHE_RAM 215 143 if CONFIG_USE_INIT … … 219 147 end 220 148 end 221 222 ##223 ## Include the secondary configuration files224 ##225 149 if CONFIG_CHIP_NAME 226 150 config chip.h -
trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
r3053 r3622 81 81 uses CONFIG_PCI_ROM_RUN 82 82 uses HW_MEM_HOLE_SIZEK 83 84 83 uses USE_DCACHE_RAM 85 84 uses DCACHE_RAM_BASE … … 90 89 uses MEM_TRAIN_SEQ 91 90 uses WAIT_BEFORE_CPUS_INIT 92 93 91 uses ENABLE_APIC_EXT_ID 94 92 uses APIC_ID_OFFSET 95 93 uses LIFT_BSP_APIC_ID 96 97 94 uses CONFIG_PCI_64BIT_PREF_MEM 98 99 95 uses HT_CHAIN_UNITID_BASE 100 96 uses HT_CHAIN_END_UNITID_BASE 101 97 uses SB_HT_CHAIN_ON_BUS0 102 98 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY 103 104 99 uses CONFIG_LB_MEM_TOPK 105 100 101 default ROM_SIZE = 512 * 1024 102 default ROM_IMAGE_SIZE = 64 * 1024 103 default FALLBACK_SIZE = 252 * 1024 104 default FAILOVER_SIZE = 4 * 1024 105 default HAVE_FALLBACK_BOOT = 1 106 default HAVE_FAILOVER_BOOT = 1 107 default HAVE_HARD_RESET = 1 108 default HAVE_PIRQ_TABLE = 1 109 default IRQ_SLOT_COUNT = 13 110 default HAVE_MP_TABLE = 1 111 default HAVE_OPTION_TABLE = 1 112 # Move the default coreboot CMOS range off of AMD RTC registers. 113 default LB_CKS_RANGE_START = 49 114 default LB_CKS_RANGE_END = 122 115 default LB_CKS_LOC = 123 116 # SMP support (only worry about 2 micro processors). 117 default CONFIG_SMP = 1 118 default CONFIG_MAX_CPUS = 2 119 default CONFIG_MAX_PHYSICAL_CPUS = 1 120 default CONFIG_LOGICAL_CPUS = 1 121 # 1G memory hole. 122 default HW_MEM_HOLE_SIZEK = 0x100000 123 # HT Unit ID offset, default is 1, the typical one. 124 default HT_CHAIN_UNITID_BASE = 0 125 # Real SB Unit ID, default is 0x20, mean don't touch it at last. 126 # default HT_CHAIN_END_UNITID_BASE = 0x10 127 # Make the SB HT chain on bus 0, default is not (0). 128 default SB_HT_CHAIN_ON_BUS0 = 2 129 # Only offset for SB chain?, default is yes(1). 130 default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 131 # default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console 132 default CONFIG_CONSOLE_VGA = 1 # For VGA console 133 default CONFIG_PCI_ROM_RUN = 1 # For VGA console 134 default USE_DCACHE_RAM = 1 135 default DCACHE_RAM_BASE = 0xc8000 136 default DCACHE_RAM_SIZE = 32 * 1024 137 default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 138 default CONFIG_USE_INIT = 0 139 default CONFIG_AP_CODE_IN_CAR = 0 140 default MEM_TRAIN_SEQ = 2 141 default WAIT_BEFORE_CPUS_INIT = 0 142 # default ENABLE_APIC_EXT_ID = 0 143 # default APIC_ID_OFFSET = 0x10 144 # default LIFT_BSP_APIC_ID = 0 145 # default CONFIG_PCI_64BIT_PREF_MEM = 1 146 default CONFIG_IOAPIC = 1 147 default MAINBOARD_PART_NUMBER = "A8N-E" 148 default MAINBOARD_VENDOR = "ASUS" 149 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x10f1 150 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x2891 151 default STACK_SIZE = 8 * 1024 152 default HEAP_SIZE = 16 * 1024 153 # Only use the option table in a normal image. 154 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) 155 default _RAMBASE = 0x00004000 156 default CONFIG_ROM_PAYLOAD = 1 157 default CC = "$(CROSS_COMPILE)gcc -m32" 158 default HOSTCC = "gcc" 159 default CONFIG_GDB_STUB = 0 160 default CONFIG_CONSOLE_SERIAL8250 = 1 161 default TTYS0_BAUD = 115200 162 default TTYS0_BASE = 0x3f8 163 default TTYS0_LCS = 0x3 164 default DEFAULT_CONSOLE_LOGLEVEL = 8 165 default MAXIMUM_CONSOLE_LOGLEVEL = 8 166 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" 106 167 107 ## ROM_SIZE is the size of boot ROM that this board will use.108 ## ---> 512 Kbytes109 default ROM_SIZE=(512*1024)110 111 ##112 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use113 ##114 default FALLBACK_SIZE=(252*1024)115 116 #FAILOVER: 4K117 default FAILOVER_SIZE=(4*1024)118 119 ###120 ### Build options121 ###122 123 ##124 ## Build code for the fallback boot125 ##126 default HAVE_FALLBACK_BOOT=1127 default HAVE_FAILOVER_BOOT=1128 129 ##130 ## Build code to reset the motherboard from coreboot131 ##132 default HAVE_HARD_RESET=1133 134 ##135 ## Build code to export a programmable irq routing table136 ##137 default HAVE_PIRQ_TABLE=1138 default IRQ_SLOT_COUNT=13139 140 ##141 ## Build code to export an x86 MP table142 ## Useful for specifying IRQ routing values143 ##144 default HAVE_MP_TABLE=1145 146 ##147 ## Build code to export a CMOS option table148 ##149 default HAVE_OPTION_TABLE=1150 151 ##152 ## Move the default coreboot cmos range off of AMD RTC registers153 ##154 default LB_CKS_RANGE_START=49155 default LB_CKS_RANGE_END=122156 default LB_CKS_LOC=123157 158 ##159 ## Build code for SMP support160 ## Only worry about 2 micro processors161 ##162 default CONFIG_SMP=1163 default CONFIG_MAX_CPUS=2164 default CONFIG_MAX_PHYSICAL_CPUS=1165 default CONFIG_LOGICAL_CPUS=1166 167 #1G memory hole168 default HW_MEM_HOLE_SIZEK=0x100000169 170 ##HT Unit ID offset, default is 1, the typical one171 default HT_CHAIN_UNITID_BASE=0172 173 ##real SB Unit ID, default is 0x20, mean dont touch it at last174 #default HT_CHAIN_END_UNITID_BASE=0x10175 176 #make the SB HT chain on bus 0, default is not (0)177 default SB_HT_CHAIN_ON_BUS0=2178 179 ##only offset for SB chain?, default is yes(1)180 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0181 182 #BTEXT Console183 #default CONFIG_CONSOLE_BTEXT=1184 185 #VGA Console186 default CONFIG_CONSOLE_VGA=1187 default CONFIG_PCI_ROM_RUN=1188 189 ##190 ## enable CACHE_AS_RAM specifics191 ##192 default USE_DCACHE_RAM=1193 #default DCACHE_RAM_BASE=0xcf000194 #default DCACHE_RAM_SIZE=0x1000195 default DCACHE_RAM_BASE=0xc8000196 default DCACHE_RAM_SIZE=0x08000197 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000198 default CONFIG_USE_INIT=0199 200 default CONFIG_AP_CODE_IN_CAR=0201 default MEM_TRAIN_SEQ=2202 default WAIT_BEFORE_CPUS_INIT=0203 204 ## APIC stuff205 #default ENABLE_APIC_EXT_ID=0206 #default APIC_ID_OFFSET=0x10207 #default LIFT_BSP_APIC_ID=0208 209 210 #default CONFIG_PCI_64BIT_PREF_MEM=1211 212 ##213 ## Build code to setup a generic IOAPIC214 ##215 default CONFIG_IOAPIC=1216 217 ##218 ## Clean up the motherboard id strings219 ##220 default MAINBOARD_PART_NUMBER="A8NE"221 default MAINBOARD_VENDOR="ASUS"222 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1223 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891224 225 ###226 ### coreboot layout values227 ###228 229 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.230 default ROM_IMAGE_SIZE = (64*1024)231 #65536232 233 ##234 ## Use a small 8K stack235 ##236 default STACK_SIZE=0x2000237 238 ##239 ## Use a small 16K heap240 ##241 default HEAP_SIZE=0x4000242 243 ##244 ## Only use the option table in a normal image245 ##246 #efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE247 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )248 249 ##250 ## Coreboot C code runs at this location in RAM251 ##252 default _RAMBASE=0x00004000253 254 ##255 ## Load the payload from the ROM256 ##257 default CONFIG_ROM_PAYLOAD = 1258 259 ###260 ### Defaults of options that you may want to override in the target config file261 ###262 263 ##264 ## The default compiler265 ##266 default CC="$(CROSS_COMPILE)gcc -m32"267 default HOSTCC="gcc"268 269 ##270 ## Disable the gdb stub by default271 ##272 default CONFIG_GDB_STUB=0273 274 ##275 ## The Serial Console276 ##277 278 # To Enable the Serial Console279 default CONFIG_CONSOLE_SERIAL8250=1280 281 ## Select the serial console baud rate282 default TTYS0_BAUD=115200283 #default TTYS0_BAUD=57600284 #default TTYS0_BAUD=38400285 #default TTYS0_BAUD=19200286 #default TTYS0_BAUD=9600287 #default TTYS0_BAUD=4800288 #default TTYS0_BAUD=2400289 #default TTYS0_BAUD=1200290 291 # Select the serial console base port292 default TTYS0_BASE=0x3f8293 294 # Select the serial protocol295 # This defaults to 8 data bits, 1 stop bit, and no parity296 default TTYS0_LCS=0x3297 298 ##299 ### Select the coreboot loglevel300 ##301 ## EMERG 1 system is unusable302 ## ALERT 2 action must be taken immediately303 ## CRIT 3 critical conditions304 ## ERR 4 error conditions305 ## WARNING 5 warning conditions306 ## NOTICE 6 normal but significant condition307 ## INFO 7 informational308 ## DEBUG 8 debug-level messages309 ## SPEW 9 Way too many details310 311 ## Request this level of debugging output312 default DEFAULT_CONSOLE_LOGLEVEL=8313 ## At a maximum only compile in this level of debugging314 default MAXIMUM_CONSOLE_LOGLEVEL=8315 316 ##317 ## Select power on after power fail setting318 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"319 320 ### End Options.lb321 168 end -
trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
r3594 r3622 77 77 static void memreset_setup(void) 78 78 { 79 /* FIXME: Nothing to do?*/79 /* Nothing to do. */ 80 80 } 81 81 82 82 static void memreset(int controllers, const struct mem_controller *ctrl) 83 83 { 84 /* FIXME: Nothing to do?*/84 /* Nothing to do. */ 85 85 } 86 86 87 87 static inline void activate_spd_rom(const struct mem_controller *ctrl) 88 88 { 89 /* FIXME: Nothing to do?*/89 /* Nothing to do. */ 90 90 } 91 91 … … 124 124 /* LPC Positive Decode 0 */ 125 125 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0); 126 /* Serial 0, Serial 1 */ 127 dword |= (1 << 0) | (1 << 1); 126 dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */ 128 127 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); 129 128 } … … 213 212 214 213 int needs_reset; 215 unsigned bsp_apicid = 0; 216 214 unsigned nodes, bsp_apicid = 0; 217 215 struct mem_controller ctrl[8]; 218 unsigned nodes; 219 220 if (bist == 0) { 216 217 if (bist == 0) 221 218 bsp_apicid = init_cpus(cpu_init_detectedx); 222 }223 219 224 220 it8712f_24mhz_clkin(); … … 238 234 wait_all_core0_started(); 239 235 #if CONFIG_LOGICAL_CPUS==1 240 / / It is said that we should start core1 after all core0 launched236 /* It is said that we should start core1 after all core0 launched. */ 241 237 start_other_cores(); 242 238 wait_all_other_cores_started(bsp_apicid); … … 244 240 245 241 needs_reset |= ht_setup_chains_x(); 246 247 242 needs_reset |= ck804_early_setup_x(); 248 243 … … 255 250 256 251 nodes = get_nodes(); 257 / /It's the time to set ctrl now;252 /* It's the time to set ctrl now. */ 258 253 fill_mem_ctrl(nodes, ctrl, spd_addr); 259 254 -
trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c
r3052 r3622 27 27 #include <string.h> 28 28 #include <stdint.h> 29 #include <stdlib.h> 29 30 #if CONFIG_LOGICAL_CPUS == 1 30 31 #include <cpu/amd/dualcore.h> 31 32 #endif 32 33 33 #include <cpu/amd/amdk8_sysconf.h> 34 34 35 /* Global variables for MB layouts and these will be shared by irqtable, 35 /* 36 * Global variables for MB layouts and these will be shared by irqtable, 36 37 * mptable and acpi_tables. 37 38 */ … … 41 42 unsigned apicid_ck804; 42 43 43 unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not 44 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 45 0x0000ff0, //no HTIO for a8n_e 44 /* 45 * Here you only need to set value in pci1234 for HT-IO that could be installed 46 * or not. You may need to preset pci1234 for HT-IO board, please refer to 47 * src/northbridge/amd/amdk8/get_sblk_pci1234.c for details. 48 */ 49 unsigned pci1234x[] = { 50 0x0000ff0, /* No HTIO for A8N-E */ 46 51 }; 47 unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 48 0x20202020, //a8n_e has only one ht-chain 52 53 /* 54 * HT Chain device num, actually it is unit id base of every ht device in 55 * chain, assume every chain only have 4 ht device at most. 56 */ 57 unsigned hcdnx[] = { 58 0x20202020, /* A8N-E has only one ht-chain */ 49 59 }; 60 50 61 unsigned bus_type[256]; 51 62 … … 56 67 void get_bus_conf(void) 57 68 { 58 unsigned apicid_base; 59 69 unsigned apicid_base, sbdn; 60 70 device_t dev; 61 unsigned sbdn;62 71 int i, j; 63 72 64 73 if (get_bus_conf_done == 1) 65 return; / /do it only once74 return; /* Do it only once. */ 66 75 67 76 get_bus_conf_done = 1; 68 77 69 sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); 70 sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); 78 /* FIXME: Is this really needed twice? */ 79 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); 80 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); 71 81 for (i = 0; i < sysconf.hc_possible_num; i++) { 72 82 sysconf.pci1234[i] = pci1234x[i]; … … 76 86 get_sblk_pci1234(); 77 87 78 sysconf.sbdn = (sysconf.hcdn[0] & 0xff); 88 sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain 79 89 sbdn = sysconf.sbdn; 80 90 81 for (i = 0; i < 6; i++) {91 for (i = 0; i < 6; i++) 82 92 bus_ck804[i] = 0; 83 } 93 for (i = 0; i < 256; i++) 94 bus_type[i] = 0; 84 95 85 for (i = 0; i < 256; i++) { 86 bus_type[i] = 0; 87 } 88 89 bus_type[0] = 1; //pci 96 bus_type[0] = 1; /* PCI */ 90 97 91 98 bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff; … … 108 115 109 116 for (i = 2; i < 6; i++) { 110 dev = 111 dev_find_slot(bus_ck804[0], 112 PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); 117 dev = dev_find_slot(bus_ck804[0], 118 PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); 113 119 if (dev) { 114 120 bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); … … 118 124 bus_type[j] = 1; 119 125 } else { 120 printk_debug 121 ("ERROR - could not find PCI %02x:%02x.0, using defaults\n", 126 printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", 122 127 bus_ck804[0], sbdn + 0x0b + i - 2); 123 128 bus_isa = bus_ck804[i - 1] + 1; … … 125 130 } 126 131 127 /*I/O APICs: APIC ID Version State Address*/128 132 #if CONFIG_LOGICAL_CPUS==1 129 133 apicid_base = get_apicid_base(3); -
trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c
r3052 r3622 21 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 22 */ 23 24 /* Documentation at: http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */25 23 26 24 #include <console/console.h> … … 64 62 unsigned long write_pirq_routing_table(unsigned long addr) 65 63 { 66 67 64 struct irq_routing_table *pirq; 68 65 struct irq_info *pirq_info; 69 unsigned slot_num; 70 uint8_t *v; 66 unsigned slot_num, sbdn; 67 uint8_t *v, sum = 0; 68 int i; 71 69 72 uint8_t sum = 0; 73 int i; 74 unsigned sbdn; 75 76 /* get_bus_conf() will find out all bus num and apic that share with 77 * mptable.c and mptable.c 70 /* get_bus_conf() will find out all bus num and APIC that share with 71 * mptable.c and mptable.c. 78 72 */ 79 73 get_bus_conf(); … … 84 78 addr &= ~15; 85 79 86 /* This table must be betweeen 0xf0000 & 0x100000 */80 /* This table must be betweeen 0xf0000 & 0x100000. */ 87 81 printk_info("Writing IRQ routing tables to 0x%x...", addr); 88 82 89 83 pirq = (void *)(addr); 90 v = (uint8_t *) 84 v = (uint8_t *)(addr); 91 85 92 86 pirq->signature = PIRQ_SIGNATURE; 93 87 pirq->version = PIRQ_VERSION; 94 95 88 pirq->rtr_bus = bus_ck804[0]; 96 89 pirq-&