Changeset 3614

Timestamp:

09/29/08 20:09:51 (7 weeks ago)

Author:

mjones

Message:

This patch for the AMD K8 allows a single DIMM to be populated in the
ChannelB slot. Previously a DIMM could only be populated in ChannelB
if there was a DIMM already in ChannelA. This patch doesn't allow unmatched
DIMMs to be populate in ChannelA and ChannelB. In an A & B configuration
the DIMM must still be matched.

Signed-off-by: Marc Jones <marc.jones@…>
Acked-by: Stefan Reinauer <stepan@…>

Location:

trunk/coreboot-v2/src/northbridge/amd/amdk8

Files:

• amdk8_f.h (modified) (1 diff)
• raminit_f.c (modified) (55 diffs)
• raminit_f_dqs.c (modified) (7 diffs)

trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_f.h

@@ -482 +482 @@
         uint8_t is_ecc;
         uint8_t is_Width128;
+        uint8_t is_64MuxMode;
         uint8_t memclk_set; // we need to use this to retrieve the mem param
-        uint8_t rsv[3];
+        uint8_t rsv[2];
 } __attribute__((packed));
 

trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c

@@ -850 +850 @@
 
 static void set_dimm_size(const struct mem_controller *ctrl,
-                         struct dimm_size *sz, unsigned index, int is_Width128)
+                         struct dimm_size *sz, unsigned index, struct mem_info *meminfo)
 {
         uint32_t base0, base1;
@@ -873 +873 @@
 
         /* Double the size if we are using dual channel memory */
-        if (is_Width128) {
+        if (meminfo->is_Width128) {
                 base0 = (base0 << 1) | (base0 & 1);
                 base1 = (base1 << 1) | (base1 & 1);
@@ -882 +882 @@
         base1 &= ~0xe007fffe;
 
-        /* Set the appropriate DIMM base address register */
-        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
-        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+        if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
+        } else {
+                /* Set the appropriate DIMM base address register */
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);
 #if QRANK_DIMM_SUPPORT == 1
-        if (sz->rank == 4) {
-                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
-                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
-        }
-#endif
+                if (sz->rank == 4) {
+                        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);
+                        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);
+                }
+#endif
+        }
 
         /* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/
@@ -904 +909 @@
 #endif
 
-                dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
-                dword &= ~(ClkDis0 >> index);
-#if QRANK_DIMM_SUPPORT == 1
-                if (sz->rank == 4) {
-                        dword &= ~(ClkDis0 >> (index+2));
-                }
-#endif
-                pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
-
-                if (is_Width128) { //Channel B
+                if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
                         dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
+                        dword &= ~(ClkDis0 >> index);
+                        pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
+
+                } else {
+                        dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A
                         dword &= ~(ClkDis0 >> index);
 #if QRANK_DIMM_SUPPORT == 1
@@ -921 +922 @@
                         }
 #endif
-                        pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
+                        pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dword);
+
+                        if (meminfo->is_Width128) { // ChannelA+B
+                                dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
+                                dword &= ~(ClkDis0 >> index);
+#if QRANK_DIMM_SUPPORT == 1
+                                if (sz->rank == 4) {
+                                        dword &= ~(ClkDis0 >> (index+2));
+                                }
+#endif
+                                pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dword);
+                        }
                 }
 
@@ -944 +956 @@
 
 static void set_dimm_cs_map(const struct mem_controller *ctrl,
-                             struct dimm_size *sz, unsigned index)
+                             struct dimm_size *sz, unsigned index,
+                             struct mem_info *meminfo)
 {
         static const uint8_t cs_map_aaa[24] = {
@@ -962 +975 @@
         uint32_t map;
 
+        if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
+                index += 2;
+        }
         map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
         map &= ~(0xf << (index * 4));
@@ -987 +1003 @@
 
 
-static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask,
+static long spd_set_ram_size(const struct mem_controller *ctrl,
                               struct mem_info *meminfo)
 {
@@ -994 +1010 @@
         for (i = 0; i < DIMM_SOCKETS; i++) {
                 struct dimm_size *sz = &(meminfo->sz[i]);
-                if (!(dimm_mask & (1 << i))) {
-                        continue;
-                }
-                spd_get_dimm_size(ctrl->channel0[i], sz);
+                u32 spd_device = ctrl->channel0[i];
+
+                if (!(meminfo->dimm_mask & (1 << i))) {
+                        if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
+                                spd_device = ctrl->channel1[i];
+                        } else {
+                                continue;
+                        }
+                }
+
+                spd_get_dimm_size(spd_device, sz);
                 if (sz->per_rank == 0) {
                         return -1; /* Report SPD error */
                 }
-                set_dimm_size(ctrl, sz, i, meminfo->is_Width128);
-                set_dimm_cs_map (ctrl, sz, i);
-        }
-        return dimm_mask;
+                set_dimm_size(ctrl, sz, i, meminfo);
+                set_dimm_cs_map (ctrl, sz, i, meminfo);
+        }
+        return meminfo->dimm_mask;
 }
 
@@ -1244 +1267 @@
                 pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
                 /* Write the new mask register */
-                 if ((canidate & 1) == 0) {  //only have 4 CSMASK
-                         pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate>>1) << 2), csmask);
-                 }
+                if ((canidate & 1) == 0) {  //only have 4 CSMASK
+                        pci_write_config32(ctrl->f2, DRAM_CSMASK + ((canidate >> 1) << 2), csmask);
+                }
 
         }
@@ -1300 +1323 @@
 
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
-                          long dimm_mask, struct mem_info *meminfo)
+                          struct mem_info *meminfo)
 {
         print_debug("disabling dimm");
         print_debug_hex8(index);
         print_debug("\r\n");
-        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
-        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
+        if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
+        } else {
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);
+                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);
 #if QRANK_DIMM_SUPPORT == 1
-        if (meminfo->sz[index].rank == 4) {
-                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), 0);
-                pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), 0);
-        }
-#endif
-
-        dimm_mask &= ~(1 << index);
-        return dimm_mask;
+                if (meminfo->sz[index].rank == 4) {
+                        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
+                        pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
+                }
+#endif
+        }
+
+        meminfo->dimm_mask &= ~(1 << index);
+        return meminfo->dimm_mask;
 }
 
 
 static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
-                                        long dimm_mask, struct mem_info *meminfo)
+                                         struct mem_info *meminfo)
 {
         int i;
@@ -1328 +1356 @@
         for (i = 0; (i < DIMM_SOCKETS); i++) {
                 int value;
-                if (!(dimm_mask & (1 << i))) {
-                        continue;
-                }
-
-                value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_TYPE);
+                u32 spd_device = ctrl->channel0[i];
+                if (!(meminfo->dimm_mask & (1 << i))) {
+                        if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
+                                spd_device = ctrl->channel1[i];
+                        } else {
+                                continue;
+                        }
+                }
+                value = spd_read_byte(spd_device, SPD_DIMM_TYPE);
                 if (value < 0) {
                         return -1;
@@ -1339 +1371 @@
                 /* Registered dimm ? */
                 value &= 0x3f;
-                if ((value == SPD_DIMM_TYPE_RDIMM) ||
-                    (value == SPD_DIMM_TYPE_mRDIMM)) {
-                        /* check SPD_MOD_ATTRIB to verify it is
-                           SPD_MOD_ATTRIB_REGADC (0x11)? */
+                if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
+                        //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
                         registered |= (1<<i);
                 }
@@ -1349 +1379 @@
         if (is_opteron(ctrl)) {
 #if 0
-                if ( registered != (dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
-                        dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
+                if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
+                        meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
 //                      die("Mixed buffered and registered dimms not supported");
                 }
@@ -1377 +1407 @@
         }
 #endif
-        return dimm_mask;
+        return meminfo->dimm_mask;
 }
 
@@ -1407 +1437 @@
 }
 
-
-static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
+static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo)
 {
         int i;
@@ -1439 +1468 @@
                 42,     /* *Minimum Auto Refresh Command Time(Trfc) */
         };
+        u32 dcl, dcm;
+
+/* S1G1 and AM2 sockets are Mod64BitMux capable. */
+#if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12
+        u8 mux_cap = 1;
+#else
+        u8 mux_cap = 0;
+#endif
+
         /* If the dimms are not in pairs do not do dual channels */
-        if ((dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
-                ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
+        if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
+                ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
                 goto single_channel;
         }
-        /* If the cpu is not capable of doing dual channels
-           don't do dual channels */
+        /* If the cpu is not capable of doing dual channels don't do dual channels */
         nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
         if (!(nbcap & NBCAP_128Bit)) {
@@ -1455 +1492 @@
                 int j;
                 /* If I don't have a dimm skip this one */
-                if (!(dimm_mask & (1 << i))) {
+                if (!(meminfo->dimm_mask & (1 << i))) {
                         continue;
                 }
@@ -1477 +1514 @@
         }
         print_spew("Enabling dual channel memory\r\n");
-        uint32_t dcl;
         dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
         dcl &= ~DCL_BurstLength32;  /*  32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
@@ -1484 +1520 @@
         pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
         meminfo->is_Width128 = 1;
-        return dimm_mask;
+        return meminfo->dimm_mask;
+
  single_channel:
-        dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
         meminfo->is_Width128 = 0;
-        return dimm_mask;
+        meminfo->is_64MuxMode = 0;
+
+        /* single dimm */
+        if ((meminfo->dimm_mask & ((1 << DIMM_SOCKETS) - 1)) !=
+           ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
+                if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
+                        /* mux capable and single dimm in channelB */
+                        if (mux_cap) {
+                                printk_spew("Enable 64MuxMode & BurstLength32\n");
+                                dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
+                                dcm |= DCM_Mode64BitMux;
+                                pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
+                                dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+                                //dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
+                                pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+                                meminfo->is_64MuxMode = 1;
+                        } else {
+                                meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
+                        }
+                }
+        } else { /* unmatched dual dimms ? */
+                /* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
+                meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
+                printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
+        }
+        return meminfo->dimm_mask;
 }
 
@@ -1634 +1695 @@
 }
 
-static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
+static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, struct mem_info *meminfo)
 {
         /* Compute the minimum cycle time for these dimms */
@@ -1671 +1732 @@
                 int latencies;
                 int latency;
-
-                if (!(dimm_mask & (1 << i))) {
-                        continue;
+                u32 spd_device = ctrl->channel0[i];
+
+                print_tx("1.1 dimm_mask:", meminfo->dimm_mask);
+                if (!(meminfo->dimm_mask & (1 << i))) {
+                        if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
+                                spd_device = ctrl->channel1[i];
+                        } else {
+                                continue;
+                        }
                 }
 
@@ -1686 +1753 @@
                 new_latency = 6;
 
-                latencies = spd_read_byte(ctrl->channel0[i], SPD_CAS_LAT);
+                latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
                 if (latencies <= 0) continue;
 
@@ -1701 +1768 @@
                                 continue;
                         }
-                        value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+                        value = spd_read_byte(spd_device, latency_indicies[index]);
                         if (value < 0) {
                                 goto hw_error;
@@ -1754 +1821 @@
         print_tx("3 min_latency:", min_latency);
 
-        for (i = 0; (i < DIMM_SOCKETS) && (ctrl->channel0[i]); i++) {
+        for (i = 0; (i < DIMM_SOCKETS); i++) {
                 int latencies;
                 int latency;
                 int index;
                 int value;
-                if (!(dimm_mask & (1 << i))) {
-                        continue;
-                }
-
-                latencies = spd_read_byte(ctrl->channel0[i], SPD_CAS_LAT);
+                u32 spd_device = ctrl->channel0[i];
+
+                if (!(meminfo->dimm_mask & (1 << i))) {
+                        if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
+                                spd_device = ctrl->channel1[i];
+                        } else {
+                                continue;
+                        }
+                }
+
+                latencies = spd_read_byte(spd_device, SPD_CAS_LAT);
                 if (latencies < 0) goto hw_error;
                 if (latencies == 0) {
@@ -1786 +1859 @@
 
                 /* Read the min_cycle_time for this latency */
-                value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]);
+                value = spd_read_byte(spd_device, latency_indicies[index]);
                 if (value < 0) goto hw_error;
 
@@ -1798 +1871 @@
                 /* Otherwise I have an error, disable the dimm */
         dimm_err:
-                dimm_mask = disable_dimm(ctrl, i, dimm_mask, meminfo);
+                meminfo->dimm_mask = disable_dimm(ctrl, i, meminfo);
         }
 
@@ -1821 +1894 @@
         pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
 
-        result.dimm_mask = dimm_mask;
+        result.dimm_mask = meminfo->dimm_mask;
         return result;
  hw_error:
@@ -1838 +1911 @@
         return valuex;
 }
-static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+static int update_dimm_Trc(const struct mem_controller *ctrl,
+                            const struct mem_param *param,
+                            int i, long dimm_mask)
 {
         unsigned clocks, old_clocks;
@@ -1844 +1919 @@
         int value;
         int value2;
-        value = spd_read_byte(ctrl->channel0[i], SPD_TRC);
+        u32 spd_device = ctrl->channel0[i];
+
+        if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
+                spd_device = ctrl->channel1[i];
+        }
+
+        value = spd_read_byte(spd_device, SPD_TRC);
         if (value < 0) return -1;
 
-                value2 = spd_read_byte(ctrl->channel0[i], SPD_TRC -1);
-                value <<= 2;
-                value += convert_to_1_4(value2>>4);
+        value2 = spd_read_byte(spd_device, SPD_TRC -1);
+        value <<= 2;
+        value += convert_to_1_4(value2>>4);
 
         value *=10;
@@ -1879 +1960 @@
         uint32_t dth;
         int value;
+        u8 ch_b = 0;
+        u32 spd_device = ctrl->channel0[i];
+
+        if (!(meminfo->dimm_mask & (1 << i)) && (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
+                spd_device = ctrl->channel1[i];
+                ch_b = 2; /* offset to channelB trfc setting */
+        }
 
         //get the cs_size --> logic dimm size
-        value = spd_read_byte(ctrl->channel0[i], SPD_PRI_WIDTH);
+        value = spd_read_byte(spd_device, SPD_PRI_WIDTH);
         if (value < 0) {
                 return -1;
@@ -1892 +1980 @@
         dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
 
-        old_clocks = ((dth >> (DTH_TRFC0_SHIFT+i*3)) & DTH_TRFC_MASK);
+        old_clocks = ((dth >> (DTH_TRFC0_SHIFT + ((i + ch_b) * 3))) & DTH_TRFC_MASK);
+
         if (old_clocks >= clocks) { // some one did it?
                 return 1;
         }
-        dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT+i*3));
-        dth |= clocks  << (DTH_TRFC0_SHIFT+i*3);
+        dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3)));
+        dth |= clocks  << (DTH_TRFC0_SHIFT + ((i + ch_b) * 3));
         pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
         return 1;
 }
 
-static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i,
+static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
                                         unsigned TT_REG,
                                         unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
@@ -1909 +1998 @@
         uint32_t dtl;
         int value;
-        value = spd_read_byte(ctrl->channel0[i], SPD_TT); //already in 1/4 ns
+        u32 spd_device = ctrl->channel0[i];
+
+        if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */
+                spd_device = ctrl->channel1[i];
+        }
+
+        value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns
         if (value < 0) return -1;
         value *=10;
@@ -1918 +2013 @@
         
         if (clocks > TT_MAX) {
-                 return 0;
+                return 0;
         }
 
@@ -1925 +2020 @@
         old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
         if (old_clocks >= clocks) { //some one did it?
-//      clocks = old_clocks;
+//              clocks = old_clocks;
                 return 1;
         }
@@ -1936 +2031 @@
 
 static int update_dimm_Trcd(const struct mem_controller *ctrl,
-                             const struct mem_param *param, int i)
-{
-        return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
-}
-
-
-static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
-{
-        return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
-}
-
-
-static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
+                             const struct mem_param *param, int i, long dimm_mask)
+{
+        return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
+}
+
+static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask)
+{
+        return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
+}