Changeset 3587 for trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c

Timestamp:

09/20/08 00:58:59 (4 months ago)

Author:

ruik

Message:

Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the

D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
whole PCI bus.

U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
does we not.

Second small change just changes a bit which controls the PSTATECTL logic.

Third change deals with the integrated VGA, which needs to be enabled early,
so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
correctly. Finally the CPU accessible framebuffer is now disabled as it is not
needed.

Signed-off-by: Rudolf Marek <r.marek@…>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@…>

Files:

• trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c (modified) (1 diff)

trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c

@@ -106 +106 @@
         pci_write_config8(dev, 0xa5, 0x3c);
 
-        /* Arbitration control 2 */
-        pci_write_config8(dev, 0xa6, 0x82);
+        /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
+        pci_write_config8(dev, 0xa6, 0x83);
 
 }