Changeset 3587

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Timestamp:
09/20/08 00:58:59 (2 months ago)
Author:
ruik
Message:

Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the

D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
whole PCI bus.

U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
does we not.

Second small change just changes a bit which controls the PSTATECTL logic.

Third change deals with the integrated VGA, which needs to be enabled early,
so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
correctly. Finally the CPU accessible framebuffer is now disabled as it is not
needed.

Signed-off-by: Rudolf Marek <r.marek@…>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@…>

Location:
trunk/coreboot-v2/src/southbridge/via/k8t890
Files:
3 modified

Legend:

Unmodified
Added
Removed

  • trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_bridge.c

    r3183 r3587  
    2525static void bridge_enable(struct device *dev) 
    2626{ 
     27        u8 tmp; 
    2728        print_debug("B188 device dump\n"); 
    28  
    2929        /* VIA recommends this, sorry no known info. */ 
    3030 
    … …  
    4545        writeback(dev, 0x3e, 0x16); 
    4646        dump_south(dev); 
     47 
     48        /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ 
     49        tmp = pci_read_config8(dev, PCI_COMMAND); 
     50        tmp &= ~0x3; 
     51        pci_write_config8(dev, PCI_COMMAND, tmp); 
     52 
    4753} 
    4854 

  • trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c

    r3183 r3587  
    6464        /* The Address Next to the Last Valid DRAM Address */ 
    6565        pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); 
     66 
     67} 
     68 
     69static void dram_enable_k8m890(struct device *dev) 
     70{ 
     71        dram_enable(dev); 
     72 
     73        /* enable VGA, so the bridges gets VGA_EN and resources are set */ 
     74        pci_write_config8(dev, 0xa1, 0x80); 
    6675} 
    6776 
    … …  
    114123        printk_debug("VIA FB proposed base: %llx\n", proposed_base); 
    115124 
    116         /* enable UMA but no FB */ 
     125        /* Step 1: enable UMA but no FB */ 
    117126        pci_write_config8(dev, 0xa1, 0x80); 
    118127 
    119         /* 27:21 goes to 7:1, 0 is enable CPU access */ 
    120         tmp = (proposed_base >> 20) | 0x1; 
    121         pci_write_config8(dev, 0xa0, tmp); 
    122  
    123         /* 31:28 goes to 3:0 */ 
    124         tmp = ((proposed_base >> 28) & 0xf); 
    125         tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4); 
    126         tmp |= 0x80; 
     128        /* Step 2: enough is just the FB size, the CPU accessible address is not needed */ 
     129        tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4) | 0x80; 
    127130        pci_write_config8(dev, 0xa1, tmp); 
    128131 
    … …  
    142145        .set_resources          = pci_dev_set_resources, 
    143146        .enable_resources       = pci_dev_enable_resources, 
    144         .enable                 = dram_enable, 
     147        .enable                 = dram_enable_k8m890, 
    145148        .init                   = dram_init_fb, 
    146149        .ops_pci                = 0, 

  • trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_host_ctrl.c

    r3183 r3587  
    106106        pci_write_config8(dev, 0xa5, 0x3c); 
    107107 
    108         /* Arbitration control 2 */ 
    109         pci_write_config8(dev, 0xa6, 0x82); 
     108        /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */ 
     109        pci_write_config8(dev, 0xa6, 0x83); 
    110110 
    111111}