- Timestamp:
- 09/19/08 23:19:46 (2 months ago)
- Files:
-
- 1 modified
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trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c
r3585 r3586 37 37 { 38 38 #if CONFIG_USE_PRINTK_IN_CAR 39 39 printk_debug("%s%08x\r\n", strval, val); 40 40 #else 41 41 print_debug(strval); print_debug_hex32(val); print_debug("\r\n"); 42 42 #endif 43 43 } … … 56 56 { 57 57 #if RAM_TIMING_DEBUG == 1 58 print_debug(strval); 58 print_debug(strval); 59 59 #endif 60 60 } … … 69 69 70 70 71 // for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data 71 /* for PCI_ADDR(0, 0x18, 2, 0x98) index, 72 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */ 72 73 /* 73 index: 74 index: 74 75 [29: 0] DctOffset (Dram Controller Offset) 75 [30:30] DctAccessWrite (Dram Controller Read/Write Select) 76 [30:30] DctAccessWrite (Dram Controller Read/Write Select) 76 77 0 = read access 77 78 1 = write access … … 82 83 Data: 83 84 [31: 0] DctOffsetData (Dram Controller Offset Data) 84 85 85 86 Read: 86 - Write the register num to DctOffset with DctAccessWrite = 0 87 - Write the register num to DctOffset with 88 DctAccessWrite = 0 87 89 - poll the DctAccessDone until it = 1 88 90 - Read the data from DctOffsetData … … 91 93 - Write register num to DctOffset with DctAccessWrite = 1 92 94 - poll the DctAccessDone untio it = 1 93 94 95 */ 95 96 … … 98 99 { 99 100 int i; 100 for (i = 0; i < max; i += 3) {101 for (i = 0; i < max; i += 3) { 101 102 device_t dev; 102 103 unsigned where; … … 113 114 static int controller_present(const struct mem_controller *ctrl) 114 115 { 115 116 return pci_read_config32(ctrl->f0, 0) == 0x11001022; 116 117 } 117 118 … … 120 121 static const unsigned int register_values[] = { 121 122 122 /* Careful set limit registers before base registers which contain the enables */ 123 /* Careful set limit registers before base registers which 124 contain the enables */ 123 125 /* DRAM Limit i Registers 124 126 * F1:0x44 i = 0 … … 239 241 * The bits with an address mask of 1 are excluded from address comparison 240 242 * [31:29] Reserved 241 * 243 * 242 244 */ 243 245 PCI_ADDR(0, 0x18, 2, 0x60), 0xe007c01f, 0x00000000, … … 246 248 PCI_ADDR(0, 0x18, 2, 0x6C), 0xe007c01f, 0x00000000, 247 249 248 249 250 250 /* DRAM Control Register 251 * F2:0x78 252 * [ 3: 0] RdPtrInit ( Read Pointer Initial Value) 251 253 * 0x03-0x00: reserved 252 254 * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO) 253 255 * 000 = reserved 254 256 * 001 = reserved 255 * 257 * 010 = 1.5 Memory Clocks 256 258 * 011 = 2 Memory Clocks 257 259 * 100 = 2.5 Memory Clocks … … 259 261 * 110 = 3.5 Memory Clocks 260 262 * 111 = Reseved 261 * [15: 7] Reserved 262 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable) 263 * Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. This bit has no effect if the DisNbClkRamp bit (F3, 0x88) is set 263 * [15: 7] Reserved 264 * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable) 265 * Enables the DDR memory clocks to be tristated when alternate VID 266 * mode is enabled. This bit has no effect if the DisNbClkRamp bit 267 * (F3, 0x88) is set 264 268 * [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time) 265 269 * 0 = 5 ms … … 268 272 * 0 = Normal DQS Receiver enable operation 269 273 * 1 = DQS receiver enable training mode 270 * [31:19] reverved 271 */ 272 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0), 273 274 /* DRAM Initialization Register 275 * F2:0x7C 276 * [15: 0] MrsAddress (Address for MRS/EMRS Commands) 277 * this field specifies the dsata driven on the DRAM address pins 15-0 for MRS and EMRS commands 278 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands) 279 * this files specifies the data driven on the DRAM bank pins for the MRS and EMRS commands 274 * [31:19] reverved 275 */ 276 PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0), 277 278 /* DRAM Initialization Register 279 * F2:0x7C 280 * [15: 0] MrsAddress (Address for MRS/EMRS Commands) 281 * this field specifies the dsata driven on the DRAM address pins 282 * 15-0 for MRS and EMRS commands 283 * [18:16] MrsBank (Bank Address for MRS/EMRS Commands) 284 * this files specifies the data driven on the DRAM bank pins for 285 * the MRS and EMRS commands 280 286 * [23:19] reverved 281 * [24:24] SendPchgAll (Send Precharge All Command) 282 * Setting this bit causes the DRAM controller to send a precharge all command. This bit is cleared by the hardware after the command completes 287 * [24:24] SendPchgAll (Send Precharge All Command) 288 * Setting this bit causes the DRAM controller to send a precharge 289 * all command. This bit is cleared by the hardware after the 290 * command completes 283 291 * [25:25] SendAutoRefresh (Send Auto Refresh Command) 284 * Setting this bit causes the DRAM controller to send an auto refresh command. This bit is cleared by the hardware after the command completes 292 * Setting this bit causes the DRAM controller to send an auto 293 * refresh command. This bit is cleared by the hardware after the 294 * command completes 285 295 * [26:26] SendMrsCmd (Send MRS/EMRS Command) 286 * Setting this bit causes the DRAM controller to send the MRS or EMRS command defined by the MrsAddress and MrsBank fields. This bit is cleared by the hardware adter the commmand completes 296 * Setting this bit causes the DRAM controller to send the MRS or 297 * EMRS command defined by the MrsAddress and MrsBank fields. This 298 * bit is cleared by the hardware adter the commmand completes 287 299 * [27:27] DeassertMemRstX (De-assert Memory Reset) 288 * Setting this bit causes the DRAM controller to de-assert the memory reset pin. This bit cannot be used to assert the memory reset pin 300 * Setting this bit causes the DRAM controller to de-assert the 301 * memory reset pin. This bit cannot be used to assert the memory 302 * reset pin 289 303 * [28:28] AssertCke (Assert CKE) 290 * setting this bit causes the DRAM controller to assert the CKE pins. This bit cannot be used to de-assert the CKE pins 304 * setting this bit causes the DRAM controller to assert the CKE 305 * pins. This bit cannot be used to de-assert the CKE pins 291 306 * [30:29] reverved 292 307 * [31:31] EnDramInit (Enable DRAM Initialization) 293 * Setting this bit puts the DRAM controller in a BIOS controlled DRAM initialization mode. BIOS must clear this bit aster DRAM initialization is complete. 294 */ 295 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0, 308 * Setting this bit puts the DRAM controller in a BIOS controlled 309 * DRAM initialization mode. BIOS must clear this bit aster DRAM 310 * initialization is complete. 311 */ 312 // PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0, 296 313 297 314 … … 299 316 * F2:0x80 300 317 * Specify the memory module size 301 * [ 3: 0] CS1/0 318 * [ 3: 0] CS1/0 302 319 * [ 7: 4] CS3/2 303 320 * [11: 8] CS5/4 … … 317 334 10: 16 10 3 :4G 318 335 11: 16 11 3 :8G 319 */336 */ 320 337 PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000, 321 338 /* DRAM Timing Low Register … … 336 353 * 10 = 5 clocks 337 354 * 11 = 6 clocks 338 355 * [ 7: 6] Reserved 339 356 * [ 9: 8] Trp (Row Precharge Time, Precharge-to-Active or Auto-Refresh) 340 357 * 00 = 3 clocks … … 345 362 * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time) 346 363 * 0 = 2 clocks for Burst Length of 32 Bytes 347 * 348 *1 = 3 clocks for Burst Length of 32 Bytes349 *5 clocks for Burst Length of 64 Bytes364 * 4 clocks for Burst Length of 64 Bytes 365 * 1 = 3 clocks for Burst Length of 32 Bytes 366 * 5 clocks for Burst Length of 64 Bytes 350 367 * [15:12] Tras (Minimum Ras# Active Time) 351 *0000 = reserved368 * 0000 = reserved 352 369 * 0001 = reserved 353 * 0010 = 5 bus clocks 354 * ... 355 * 1111 = 18 bus clocks 356 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto refresh of the same bank) 370 * 0010 = 5 bus clocks 371 * ... 372 * 1111 = 18 bus clocks 373 * [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto 374 * refresh of the same bank) 357 375 * 0000 = 11 bus clocks 358 376 * 0010 = 12 bus clocks 359 377 * ... 360 378 * 1110 = 25 bus clocks 361 379 * 1111 = 26 bus clocks 362 * [21:20] Twr (Write Recovery Time, From the last data to precharge, writes can go back-to-back) 363 * 00 = 3 bus clocks 364 * 01 = 4 bus clocks 365 * 10 = 5 bus clocks 366 * 11 = 6 bus clocks 367 * [23:22] Trrd (Active-to-active (Ras#-to-Ras#) Delay of different banks) 368 * 00 = 2 bus clocks 369 * 01 = 3 bus clocks 370 * 10 = 4 bus clocks 371 * 11 = 5 bus clocks 372 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, BIOS should set it to reduce the power consumption) 373 * Bit F(1207) M2 Package S1g1 Package 374 * 0 N/A MA1_CLK1 N/A 380 * [21:20] Twr (Write Recovery Time, From the last data to precharge, 381 * writes can go back-to-back) 382 * 00 = 3 bus clocks 383 * 01 = 4 bus clocks 384 * 10 = 5 bus clocks 385 * 11 = 6 bus clocks 386 * [23:22] Trrd (Active-to-active(Ras#-to-Ras#) Delay of different banks) 387 * 00 = 2 bus clocks 388 * 01 = 3 bus clocks 389 * 10 = 4 bus clocks 390 * 11 = 5 bus clocks 391 * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, 392 * BIOS should set it to reduce the power consumption) 393 * Bit F(1207) M2 Package S1g1 Package 394 * 0 N/A MA1_CLK1 N/A 375 395 * 1 N/A MA0_CLK1 MA0_CLK1 376 396 * 2 MA3_CLK N/A N/A 377 397 * 3 MA2_CLK N/A N/A 378 398 * 4 MA1_CLK MA1_CLK0 N/A … … 395 415 * 111 = 9 bus clocks 396 416 * [ 7: 7] Reserved 397 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, minium write-to-read delay when both access the same chip select) 398 * 00 = Reserved 399 * 01 = 1 bus clocks 400 * 10 = 2 bus clocks 401 * 11 = 3 bus clocks 402 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum write-to-read delay when accessing two different DIMMs) 403 * 00 = 0 bus clocks 404 * 01 = 1 bus clocks 405 * 10 = 2 bus clocks 406 * 11 = 3 bus clocks 407 * [13:12] Twrwr (Write to Write Timing) 408 * 00 = 1 bus clocks ( 0 idle cycle on the bus) 409 * 01 = 2 bus clocks ( 1 idle cycle on the bus) 410 * 10 = 3 bus clocks ( 2 idle cycles on the bus) 411 * 11 = Reserved 412 * [15:14] Trdrd ( Read to Read Timing) 413 * 00 = 2 bus clocks ( 1 idle cycle on the bus) 414 * 01 = 3 bus clocks ( 2 idle cycles on the bus) 415 * 10 = 4 bus clocks ( 3 idle cycles on the bus) 416 * 11 = 5 bus clocks ( 4 idel cycles on the bus) 417 * [17:16] Tref (Refresh Rate) 418 * 00 = Undefined behavior 419 * 01 = Reserved 420 * 10 = Refresh interval of 7.8 microseconds 421 * 11 = Refresh interval of 3.9 microseconds 417 * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, 418 * minium write-to-read delay when both access the same chip select) 419 * 00 = Reserved 420 * 01 = 1 bus clocks 421 * 10 = 2 bus clocks 422 * 11 = 3 bus clocks 423 * [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum 424 * write-to-read delay when accessing two different DIMMs) 425 * 00 = 0 bus clocks 426 * 01 = 1 bus clocks 427 * 10 = 2 bus clocks 428 * 11 = 3 bus clocks 429 * [13:12] Twrwr (Write to Write Timing) 430 * 00 = 1 bus clocks ( 0 idle cycle on the bus) 431 * 01 = 2 bus clocks ( 1 idle cycle on the bus) 432 * 10 = 3 bus clocks ( 2 idle cycles on the bus) 433 * 11 = Reserved 434 * [15:14] Trdrd ( Read to Read Timing) 435 * 00 = 2 bus clocks ( 1 idle cycle on the bus) 436 * 01 = 3 bus clocks ( 2 idle cycles on the bus) 437 * 10 = 4 bus clocks ( 3 idle cycles on the bus) 438 * 11 = 5 bus clocks ( 4 idel cycles on the bus) 439 * [17:16] Tref (Refresh Rate) 440 * 00 = Undefined behavior 441 * 01 = Reserved 442 * 10 = Refresh interval of 7.8 microseconds 443 * 11 = Refresh interval of 3.9 microseconds 422 444 * [19:18] Reserved 423 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0, based on DRAM density and speed) 424 * 000 = 75 ns (all speeds, 256Mbit) 425 * 001 = 105 ns (all speeds, 512Mbit) 426 * 010 = 127.5 ns (all speeds, 1Gbit) 427 * 011 = 195 ns (all speeds, 2Gbit) 428 * 100 = 327.5 ns (all speeds, 4Gbit) 429 * 101 = reserved 430 * 110 = reserved 431 * 111 = reserved 432 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1, based on DRAM density and speed) 433 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2, based on DRAM density and speed) 434 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3, based on DRAM density and speed) 445 * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0, 446 * based on DRAM density and speed) 447 * 000 = 75 ns (all speeds, 256Mbit) 448 * 001 = 105 ns (all speeds, 512Mbit) 449 * 010 = 127.5 ns (all speeds, 1Gbit) 450 * 011 = 195 ns (all speeds, 2Gbit) 451 * 100 = 327.5 ns (all speeds, 4Gbit) 452 * 101 = reserved 453 * 110 = reserved 454 * 111 = reserved 455 * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1, 456 * based on DRAM density and speed) 457 * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2, 458 * based on DRAM density and speed) 459 * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3, 460 * based on DRAM density and speed) 435 461 */ 436 462 PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8), … … 438 464 * F2:0x90 439 465 * [ 0: 0] InitDram (Initialize DRAM) 440 * 1 = write 1 cause DRAM controller to execute the DRAM initialization, when done it read to 0 466 * 1 = write 1 cause DRAM controller to execute the DRAM 467 * initialization, when done it read to 0 441 468 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command ) 442 * 1 = write 1 causes the DRAM controller to bring the DRAMs out fo self refresh mode 469 * 1 = write 1 causes the DRAM controller to bring the DRAMs out 470 * for self refresh mode 443 471 * [ 3: 2] Reserved 444 472 * [ 5: 4] DramTerm (DRAM Termination) 445 *00 = On die termination disabled446 *01 = 75 ohms447 *10 = 150 ohms448 *11 = 50 ohms473 * 00 = On die termination disabled 474 * 01 = 75 ohms 475 * 10 = 150 ohms 476 * 11 = 50 ohms 449 477 * [ 6: 6] Reserved 450 478 * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode) … … 452 480 * 1 = Weak drive strength mode 453 481 * [ 8: 8] ParEn (Parity Enable) 454 * 1 = Enable address parity computation output, PAR, and enables the parity error input, ERR 455 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable) 456 * 1 = Enable high temperature ( two times normal ) self refresh rate 482 * 1 = Enable address parity computation output, PAR, 483 * and enables the parity error input, ERR 484 * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable) 485 * 1 = Enable high temperature ( two times normal ) 486 * self refresh rate 457 487 * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes) 458 488 * 0 = 64-byte mode 459 489 * 1 = 32-byte mode 460 * [11:11] Width128 ( Width of DRAM interface) 490 * [11:11] Width128 ( Width of DRAM interface) 461 491 * 0 = the controller DRAM interface is 64-bits wide 462 492 * 1 = the controller DRAM interface is 128-bits wide 463 464 465 466 467 468 493 * [12:12] X4Dimm (DIMM 0 is x4) 494 * [13:13] X4Dimm (DIMM 1 is x4) 495 * [14:14] X4Dimm (DIMM 2 is x4) 496 * [15:15] X4Dimm (DIMM 3 is x4) 497 * 0 = DIMM is not x4 498 * 1 = x4 DIMM present 469 499 * [16:16] UnBuffDimm ( Unbuffered DIMMs) 470 500 * 0 = Buffered DIMMs … … 472 502 * [18:17] Reserved 473 503 * [19:19] DimmEccEn ( DIMM ECC Enable ) 474 1 = ECC checking is being enabled for all DIMMs on the DRAM controller ( Through F3 0x44[EccEn]) 504 * 1 = ECC checking is being enabled for all DIMMs on the DRAM 505 * controller ( Through F3 0x44[EccEn]) 475 506 * [31:20] Reserved 476 507 */ … … 482 513 * 001 = 266MHz 483 514 * 010 = 333MHz 484 515 * 011 = reserved 485 516 * 1xx = reserved 486 517 * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid) 487 * 1 = BIOS need to set the bit when setting up MemClkFreq to the proper value 518 * 1 = BIOS need to set the bit when setting up MemClkFreq to 519 * the proper value 488 520 * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency) 489 * 0000 = 0 ns 490 * ... 491 * 1111 = 15 ns 492 * [11: 8] Reserved 493 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 registered DIMMs are present in the system 494 * 0 = DM pins function as data mask pins 495 * 1 = DM pins function as read DQS pins 496 * [13:13] Reserved 497 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit is set, the DRAM controller is disabled, and interface in low power state 498 * 0 = Enabled (default) 499 * 1 = Disabled 500 * [15:15] PowerDownEn ( Power Down Mode Enable ) 501 * 0 = Disabled (default) 502 * 1 = Enabled 503 * [16:16] PowerDown ( Power Down Mode ) 504 * 0 = Channel CKE Control 505 * 1 = Chip Select CKE Control 506 * [17:17] FourRankSODimm (Four Rank SO-DIMM) 507 * 1 = this bit is set by BIOS to indicate that a four rank SO-DIMM is present 508 * [18:18] FourRankRDimm (Four Rank Registered DIMM) 509 * 1 = this bit is set by BIOS to indicate that a four rank registered DIMM is present 521 * 0000 = 0 ns 522 * ... 523 * 1111 = 15 ns 524 * [11: 8] Reserved 525 * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 526 * registered DIMMs are present in the system 527 * 0 = DM pins function as data mask pins 528 * 1 = DM pins function as read DQS pins 529 * [13:13] Reserved 530 * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit 531 * is set, the DRAM controller is disabled, and interface in low power 532 * state 533 * 0 = Enabled (default) 534 * 1 = Disabled 535 * [15:15] PowerDownEn ( Power Down Mode Enable ) 536 * 0 = Disabled (default) 537 * 1 = Enabled 538 * [16:16] PowerDown ( Power Down Mode ) 539 * 0 = Channel CKE Control 540 * 1 = Chip Select CKE Control 541 * [17:17] FourRankSODimm (Four Rank SO-DIMM) 542 * 1 = this bit is set by BIOS to indicate that a four rank 543 * SO-DIMM is present 544 * [18:18] FourRankRDimm (Four Rank Registered DIMM) 545 * 1 = this bit is set by BIOS to indicate that a four rank 546 * registered DIMM is present 510 547 * [19:19] Reserved 511 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode)) 512 * 0 = DRAM address and control signals are driven for one MEMCLK cycle 513 * 1 = One additional MEMCLK of setup time is provided on all DRAM address and control signals except CS, CKE, and ODT; i.e., these signals are drivern for two MEMCLK cycles rather than one 514 * [21:21] Reserved 515 * [22:22] BankSwizzleMode ( Bank Swizzle Mode), 516 * 0 = Disabled (default) 517 * 1 = Enabled 518 * [23:23] Reserved 548 * [20:20] SlowAccessMode (Slow Access Mode (2T Mode)) 549 * 0 = DRAM address and control signals are driven for one 550 * MEMCLK cycle 551 * 1 = One additional MEMCLK of setup time is provided on all 552 * DRAM address and control signals except CS, CKE, and ODT; 553 * i.e., these signals are drivern for two MEMCLK cycles 554 * rather than one 555 * [21:21] Reserved 556 * [22:22] BankSwizzleMode ( Bank Swizzle Mode), 557 * 0 = Disabled (default) 558 * 1 = Enabled 559 * [23:23] Reserved 519 560 * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum) 520 561 * 0000 = No bypass; the oldest request is never bypassed 521 562 * 0001 = The oldest request may be bypassed no more than 1 time 522 563 * ... 523 * 1111 = The oldest request may be bypassed no more than 15 times 524 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than 4 banks in a 8 bank device are activated 525 * 0000 = No tFAW window restriction 526 * 0001 = 8 MEMCLK cycles 527 * 0010 = 9 MEMCLK cycles 528 * ... 529 * 1101 = 20 MEMCLK cycles 564 * 1111 = The oldest request may be bypassed no more than 15\ 565 * times 566 * [31:28] FourActWindow ( Four Bank Activate Window) , not more than 567 * 4 banks in a 8 bank device are activated 568 * 0000 = No tFAW window restriction 569 * 0001 = 8 MEMCLK cycles 570 * 0010 = 9 MEMCLK cycles 571 * ... 572 * 1101 = 20 MEMCLK cycles 530 573 * 111x = reserved 531 574 */ … … 533 576 /* DRAM Delay Line Register 534 577 * F2:0xa0 535 * [ 0: 0] MemClrStatus (Memory Clear Status) : ---------Readonly 536 * when set, this bit indicates that the memory clear function is complete. Only clear by reset. BIOS should not write or read the DRAM until this bit is set by hardware 578 * [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly 579 * when set, this bit indicates that the memory clear function 580 * is complete. Only clear by reset. BIOS should not write or 581 * read the DRAM until this bit is set by hardware 537 582 * [ 1: 1] DisableJitter ( Disable Jitter) 538 * When set the DDR compensation circuit will not change the values unless the change is more than one step from the current value 583 * When set the DDR compensation circuit will not change the 584 * values unless the change is more than one step from the 585 * current value 539 586 * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count) 540 587 * 00 = 2 … … 543 590 * 11 = 16 544 591 * [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable) 545 * 1 When bit enables support for mismatched DIMMs when using 128-bit DRAM interface, the Width128 no effect, only for M2 and s1g1 592 * 1 When bit enables support for mismatched DIMMs when using 593 * 128-bit DRAM interface, the Width128 no effect, only for 594 * AM2 and s1g1 546 595 * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable) 547 * When set to 1, indicates that each entry in the page tables dynamically adjusts the idle cycle limit based on page Conflict/Page Miss (PC/PM) traffic 596 * When set to 1, indicates that each entry in the page tables