| 1 | | /* This should be done by Eric |
| 2 | | 2004.11 yhlu add 4 rank DIMM support |
| 3 | | 2004.12 yhlu add D0 support |
| 4 | | 2005.02 yhlu add E0 memory hole support |
| 5 | | 2005.10 yhlu make it support DDR2 only |
| | 1 | /* |
| | 2 | * This file is part of the coreboot project. |
| | 3 | * |
| | 4 | * Copyright (C) 2002 Linux Networx |
| | 5 | * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx) |
| | 6 | * Copyright (C) 2004 YingHai Lu |
| | 7 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| | 8 | * |
| | 9 | * This program is free software; you can redistribute it and/or modify |
| | 10 | * it under the terms of the GNU General Public License as published by |
| | 11 | * the Free Software Foundation; version 2 of the License. |
| | 12 | * |
| | 13 | * This program is distributed in the hope that it will be useful, |
| | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| | 16 | * GNU General Public License for more details. |
| | 17 | * |
| | 18 | * You should have received a copy of the GNU General Public License |
| | 19 | * along with this program; if not, write to the Free Software |
| | 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 2056 | | dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); |
| 2057 | | dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT); |
| 2058 | | dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT); |
| 2059 | | pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); |
| | 2071 | |
| | 2072 | |
| | 2073 | #if DIMM_SUPPORT == 0x0204 |
| | 2074 | odt = 0x2; /* 150 ohms */ |
| | 2075 | #endif |
| | 2076 | |
| | 2077 | dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); |
| | 2078 | dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT); |
| | 2079 | dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT); |
| | 2080 | pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); |
| | 2259 | #endif |
| | 2260 | |
| | 2261 | #if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ |
| | 2262 | dword = 0x00111222; |
| | 2263 | dwordx = 0x002F2F00; |
| | 2264 | |
| | 2265 | switch (meminfo->memclk_set) { |
| | 2266 | case DCH_MemClkFreq_200MHz: /* nothing to be set here */ |
| | 2267 | break; |
| | 2268 | case DCH_MemClkFreq_266MHz: |
| | 2269 | if ((meminfo->single_rank_mask == 0) |
| | 2270 | && (meminfo->x4_mask == 0) && (meminfo->x16_mask)) |
| | 2271 | dwordx = 0x002C2C00; /* Double rank x8 */ |
| | 2272 | /* else SRx16, SRx8, DRx16 == 0x002F2F00 */ |
| | 2273 | break; |
| | 2274 | case DCH_MemClkFreq_333MHz: |
| | 2275 | if ((meminfo->single_rank_mask == 1) |
| | 2276 | && (meminfo->x16_mask == 1)) /* SR x16 */ |
| | 2277 | dwordx = 0x00272700; |
| | 2278 | else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0) |
| | 2279 | && (meminfo->single_rank_mask == 0)) { /* DR x8 */ |
| | 2280 | SlowAccessMode = 1; |
| | 2281 | dwordx = 0x00002800; |
| | 2282 | } else { /* SR x8, DR x16 */ |
| | 2283 | dwordx = 0x002A2A00; |
| | 2284 | } |
| | 2285 | break; |
| | 2286 | case DCH_MemClkFreq_400MHz: |
| | 2287 | if ((meminfo->single_rank_mask == 1) |
| | 2288 | && (meminfo->x16_mask == 1)) /* SR x16 */ |
| | 2289 | dwordx = 0x00292900; |
| | 2290 | else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0) |
| | 2291 | && (meminfo->single_rank_mask == 0)) { /* DR x8 */ |
| | 2292 | SlowAccessMode = 1; |
| | 2293 | dwordx = 0x00002A00; |
| | 2294 | } else { /* SR x8, DR x16 */ |
| | 2295 | dwordx = 0x002A2A00; |
| | 2296 | } |
| | 2297 | break; |
| | 2298 | } |
