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Changeset 3556 for trunk

Timestamp:

09/01/08 03:48:07 (3 months ago)

Author:

stuge

Message:

This patch gets the Epia-CN working without ACPI or APIC.

All devices work, no irq storms. Enjoy.

Signed-off-by: Bari Ari <bari@…>
Acked-by: Peter Stuge <peter@…>

Location:

trunk/coreboot-v2

Files:

r3334	r3556
99	99	register "ide1_80pin_cable" = "0"
100	100	device pci f.0 on end # IDE
101		register "fn_ctrl_lo" = "0x8a"
102		register "fn_ctrl_hi" = "0x9d"
103		device pci 10.0 on end # USB 1.1
104		device pci 10.1 on end # USB 1.1
105		device pci 10.2 on end # USB 1.1
106		device pci 10.3 on end # USB 1.1
	101	register "fn_ctrl_lo" = "0x80"
	102	register "fn_ctrl_hi" = "0x1d"
	103	device pci 10.0 on end # OHCI
	104	device pci 10.1 on end # OHCI
	105	device pci 10.2 on end # OHCI
	106	device pci 10.3 on end # OHCI
	107	device pci 10.4 on end # EHCI
	108	device pci 10.5 on end # UDCI
107	109	device pci 11.0 on # Southbridge LPC
108	110	chip superio/via/vt1211 # Super I/O

r3334	r3556
95	95	default CONFIG_ROM_PAYLOAD = 1
96	96	default CROSS_COMPILE = ""
97		default CC = "$(CROSS_COMPILE)gcc -m32"
	97	default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
98	98	default HOSTCC = "gcc"
99	99

r3334	r3556
56	56	device_t dev;
57	57	u8 reg;
	58
	59	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
	60	if (dev == PCI_DEV_INVALID)
	61	die("Southbridge not found!!!\n");
58	62
59		/*
60		* If I enable SATA, FILO will not find the IDE disk, so I'll disable
61		* SATA here. To not conflict with PCI spec, I'll move IDE device
62		* from 00:0f.1 to 00:0f.0.
	63	/* bit=0 means enable function (per CX700 datasheet)
	64	* 5 16.1 USB 2
	65	* 4 16.0 USB 1
	66	* 3 15.0 SATA and PATA
	67	* 2 16.2 USB 3
	68	* 1 16.4 USB EHCI
63	69	*/
64		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
65		PCI_DEVICE_ID_VIA_VT6420_SATA), 0);
66		if (dev != PCI_DEV_INVALID) {
67		/* Enable PATA. */
68		reg = pci_read_config8(dev, 0xd1);
69		reg \|= 0x08;
70		pci_write_config8(dev, 0xd1, reg);
71		reg = pci_read_config8(dev, 0x49);
72		reg \|= 0x80;
73		pci_write_config8(dev, 0x49, reg);
74		} else {
75		print_debug("No SATA device\r\n");
76		}
	70	pci_write_config8(dev, 0x50, 0x80);
77	71
78		/* Disable SATA, and PATA device will be 00:0f.0. */
79		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
80		PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
81		if (dev == PCI_DEV_INVALID)
82		die("Southbridge not found!!!\r\n");
83		reg = pci_read_config8(dev, 0x50);
84		reg \|= 0x08;
85		pci_write_config8(dev, 0x50, reg);
	72	/* bit=1 means enable internal function (per CX700 datasheet)
	73	* 3 Internal RTC
	74	* 2 Internal PS2 Mouse
	75	* 1 Internal KBC Configuration
	76	* 0 Internal Keyboard Controller
	77	*/
	78	pci_write_config8(dev, 0x51, 0x1d);
86	79	}
87	80

r3334	r3556
367	367	pci_write_config8(ctrl->d0f3, 0xed, 0x10);
368	368
369		/* SMM and APIC de~~ocoding, we do~~not use SMM */
	369	/* SMM and APIC decoding, we do not use SMM */
370	370	reg = 0x29;
371	371	pci_write_config8(ctrl->d0f3, 0x86, reg);

r3113	r3556
46	46
47	47	print_debug("Copying BOCHS Bios to 0xf000\n");
48		/* Copy the BOCHs BIOS from 0xFFFFFFFF - ROM_SIZE - BOCHs size (64k) to 0xf0000
49		This is for compatibility with the VGA ROM's BIOS callbacks */
50		memcpy(0xf0000, (0x~~FFFFFFFF - ROM_SIZE - 0x10000~~), 0x10000);
	48	/* Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
	49	* This is for compatibility with the VGA ROM's BIOS callbacks */
	50	memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000);
51	51
52	52	printk_debug("Initializing VGA\n");
53	53
54		~~pci_write_config8(dev, 0x3c, 0xb);~~
55
56	54	/* Set memory rate to 200MHz */
57	55	outb(0x3d, CRTM_INDEX);
…	…
72	70	pci_write_config32(dev,0x10, 0xf4000008);
73	71	pci_write_config32(dev,0x14, 0xfb000000);
74		~~pci_write_config8(dev, 0x3e, 0x02);~~
75		~~pci_write_config8(dev, 0x3c, 0x0a);~~
76	72
77	73

r3369	r3556
80	80
81	81	/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
82		~~/* Extend ROM decode to 1MB FFC00000 - FFFFFFFF */~~
83		~~pci_write_config8(dev, 0x41, 0x7f);~~
84	82	}
85	83

r3052	r3556
245	245	pci_write_config8(dev, 0x6C, enables);
246	246
247		/* FIXME: Map 4MB of flash into the address space,
248		* this should be in CAR call.
249		*/
250		/* pci_write_config8(dev, 0x41, 0x7f); */
	247	/*
	248	* ROM decode
	249	* bit range
	250	* 7 000E0000h-000EFFFFh
	251	* 6 FFF00000h-FFF7FFFFh
	252	* 5 FFE80000h-FFEFFFFFh
	253	* 4 FFE00000h-FFE7FFFFh
	254	* 3 FFD80000h-FFDFFFFFh
	255	* 2 FFD00000h-FFD7FFFFh
	256	* 1 FFC80000h-FFCFFFFFh
	257	* 0 FFC00000h-FFC7FFFFh
	258	* So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
	259	*/
	260	pci_write_config8(dev, 0x41, 0x7f);
251	261
252	262	/* Set bit 6 of 0x40 (I/O recovery time).
…	…
272	282	pci_write_config8(dev, 0x59, 0x80);
273	283
274		/* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */
275		pci_write_config8(dev, 0x5B, 0xb);
	284	/*
	285	* bit meaning
	286	* 3 Bypass APIC De-Assert Message (1=Enable)
	287	* 1 possibly "INTE#, INTF#, INTG#, INTH# as PCI"
	288	* bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
	289	* 0 Dynamic Clock Gating Main Switch (1=Enable)
	290	*/
	291	pci_write_config8(dev, 0x5b, 0x9);
276	292
277	293	/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */

r3334	r3556
23	23	mainboard via/epia-cn
24	24
	25	option MAXIMUM_CONSOLE_LOGLEVEL=8
	26	option DEFAULT_CONSOLE_LOGLEVEL=8
	27	option CONFIG_CONSOLE_SERIAL8250=1
	28
	29	# coreboot C code runs at this location in RAM
	30	option _RAMBASE=0x00004000
	31
25	32	#
26	33	# Generate the final ROM like this: