Changeset 3433

Timestamp:

07/23/08 23:04:03 (2 months ago)

Author:

mjones

Message:

Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).

Signed-off-by: Marc Jones <marc.jones@…>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@…>

Location:

trunk/coreboot-v2/src/northbridge/amd/amdmct

Files:

• amddefs.h (modified) (1 diff)
• mct/mct_d.c (modified) (4 diffs)

trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h

@@ -54 +54 @@
 #define AMD_DR_Ax       (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
 #define AMD_DR_Bx       (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA)
+#define AMD_DR_LT_B2    (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
 #define AMD_DR_LT_B3    (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
 #define AMD_DR_GT_B0    (AMD_DR_ALL & ~(AMD_DR_B0))

trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c

@@ -2402 +2402 @@
         // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
 
-        /* Disable auto refresh before Dram init when in ganged mode */
-        if (pDCTstat->GangedMode) {
-                val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
-                val |= 1 << DisAutoRefresh;
-                Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
+        /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */
+        if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+                if (pDCTstat->GangedMode) {
+                        val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
+                        val |= 1 << DisAutoRefresh;
+                        Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
+                }
         }
 
@@ -2412 +2414 @@
 
         /* Re-enable auto refresh after Dram init when in ganged mode
-         * to ensure both DCTs are in sync
+         * to ensure both DCTs are in sync (Erratum 278)
          */
 
-        if (pDCTstat->GangedMode) {
-                do {
-                        val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
-                } while (!(val & (1 << InitDram)));
-
-                WaitRoutine_D(50);
-
-                val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
-                val &= ~(1 << DisAutoRefresh);
-                val |= 1 << DisAutoRefresh;
-                val &= ~(1 << DisAutoRefresh);
+        if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+                if (pDCTstat->GangedMode) {
+                        do {
+                                val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
+                        } while (!(val & (1 << InitDram)));
+
+                        WaitRoutine_D(50);
+
+                        val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
+                        val &= ~(1 << DisAutoRefresh);
+                        val |= 1 << DisAutoRefresh;
+                        val &= ~(1 << DisAutoRefresh);
+                }
         }
 }
@@ -3793 +3797 @@
         u8 valid = 0;
 
-        /* FIXME: Skip reset DLL for B3 */
+        /* Skip reset DLL for B3 */
+        if (pDCTstat->LogicalCPUID & AMD_DR_B3) {
+                return;
+        }
 
         addr = HWCR;
@@ -3886 +3893 @@
         u32 dev = pDCTstat->dev_dct;
 
-        /* FIXME: Add B3 */
-        if (pDCTstat->LogicalCPUID & AMD_DR_B2) {
+        if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) {
                 mct_Wait(10000);        /* Wait 50 us*/
                 val = Get_NB32(dev, 0x110);