Changeset 3423
- Timestamp:
- 07/16/08 23:09:31 (3 months ago)
- Location:
- trunk/coreboot-v2/src/northbridge/amd/amdht
- Files:
-
- 3 modified
Legend:
- Unmodified
- Added
- Removed
-
trunk/coreboot-v2/src/northbridge/amd/amdht/h3ffeat.h
r3052 r3423 2 2 * This file is part of the coreboot project. 3 3 * 4 * Copyright (C) 2007 Advanced Micro Devices, Inc.4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. 5 5 * 6 6 * This program is free software; you can redistribute it and/or modify -
trunk/coreboot-v2/src/northbridge/amd/amdht/h3finit.c
r3052 r3423 254 254 255 255 if (targetNode == 0) 256 return; / / BSP has no predecessor, stop257 258 / / Search for the link that connects targetNode to its predecessor256 return; /* BSP has no predecessor, stop */ 257 258 /* Search for the link that connects targetNode to its predecessor */ 259 259 currentPair = 0; 260 260 while (pDat->PortList[currentPair*2+1].NodeID != targetNode) … … 267 267 predecessorLink = pDat->PortList[currentPair*2].Link; 268 268 269 / / Recursively call self to ensure the route from the BSP to the Predecessor270 / / Node is established269 /* Recursively call self to ensure the route from the BSP to the Predecessor */ 270 /* Node is established */ 271 271 routeFromBSP(predecessorNode, actualTarget, pDat); 272 272 … … 602 602 if (i != nodecnt) 603 603 { 604 / / Keep building the permutation604 /* Keep building the permutation */ 605 605 for (j = 0; j < nodecnt; j++) 606 606 { 607 / / Make sure the degree matches607 /* Make sure the degree matches */ 608 608 if (pDat->sysDegree[i] != pDat->dbDegree[j]) 609 609 continue; 610 610 611 / / Make sure that j hasn't been used yet (ought to use a "used"612 / / array instead, might be faster)611 /* Make sure that j hasn't been used yet (ought to use a "used" */ 612 /* array instead, might be faster) */ 613 613 for (k = 0; k < i; k++) 614 614 { … … 624 624 return FALSE; 625 625 } else { 626 / / Test to see if the permutation is isomorphic626 /* Test to see if the permutation is isomorphic */ 627 627 for (j = 0; j < nodecnt; j++) 628 628 { … … 686 686 if (graphHowManyNodes(pSelected) == size) 687 687 { 688 / / Build Degree vector and Adjency Matrix for this entry688 /* Build Degree vector and Adjency Matrix for this entry */ 689 689 for (i = 0; i < size; i++) 690 690 { … … 704 704 } 705 705 if (isoMorph(0, pDat)) 706 break; // A matching topology was found706 break; /* A matching topology was found */ 707 707 } 708 708 … … 713 713 if (pSelected != NULL) 714 714 { 715 / / Compute the reverse Permutation715 /* Compute the reverse Permutation */ 716 716 for (i = 0; i < size; i++) 717 717 { … … 719 719 } 720 720 721 / / Start with the last discovered node, and move towards the BSP721 /* Start with the last discovered node, and move towards the BSP */ 722 722 for (i = size-1; i >= 0; i--) 723 723 { … … 1172 1172 { 1173 1173 if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(node, link)) 1174 continue; / / Skip the link1174 continue; /* Skip the link */ 1175 1175 1176 1176 if (node == 0 && link == compatLink) … … 1209 1209 for (i = 0; i < pDat->TotalLinks*2; i += 2) 1210 1210 { 1211 ASSERT(pDat->PortList[i].Type < 2 && pDat->PortList[i].Link < pDat->nb->maxLinks); / / Data validation1212 ASSERT(pDat->PortList[i+1].Type < 2 && pDat->PortList[i+1].Link < pDat->nb->maxLinks); / / data validation1213 ASSERT(!(pDat->PortList[i].Type == PORTLIST_TYPE_IO && pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)); / / ensure src is closer to the bsp than dst1211 ASSERT(pDat->PortList[i].Type < 2 && pDat->PortList[i].Link < pDat->nb->maxLinks); /* Data validation */ 1212 ASSERT(pDat->PortList[i+1].Type < 2 && pDat->PortList[i+1].Link < pDat->nb->maxLinks); /* data validation */ 1213 ASSERT(!(pDat->PortList[i].Type == PORTLIST_TYPE_IO && pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU)); /* ensure src is closer to the bsp than dst */ 1214 1214 1215 1215 /* Regang is false unless we pass all conditions below */ … … 1218 1218 1219 1219 if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) 1220 continue; // Only process cpu to cpu links1220 continue; /* Only process cpu to cpu links */ 1221 1221 1222 1222 for (j = i+2; j < pDat->TotalLinks*2; j += 2) 1223 1223 { 1224 1224 if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) ) 1225 continue; / / Only process cpu to cpu links1225 continue; /* Only process cpu to cpu links */ 1226 1226 1227 1227 if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) 1228 continue; / / Links must be from the same source1228 continue; /* Links must be from the same source */ 1229 1229 1230 1230 if (pDat->PortList[i+1].NodeID != pDat->PortList[j+1].NodeID) 1231 continue; / / Link must be to the same target1231 continue; /* Link must be to the same target */ 1232 1232 1233 1233 if ((pDat->PortList[i].Link & 3) != (pDat->PortList[j].Link & 3)) 1234 continue; / / Ensure same source base port1234 continue; /* Ensure same source base port */ 1235 1235 1236 1236 if ((pDat->PortList[i+1].Link & 3) != (pDat->PortList[j+1].Link & 3)) 1237 continue; / / Ensure same destination base port1237 continue; /* Ensure same destination base port */ 1238 1238 1239 1239 if ((pDat->PortList[i].Link & 4) != (pDat->PortList[i+1].Link & 4)) 1240 continue; / / Ensure sublink0 routes to sublink01241 1242 ASSERT((pDat->PortList[j].Link & 4) == (pDat->PortList[j+1].Link & 4)); / / (therefore sublink1 routes to sublink1)1240 continue; /* Ensure sublink0 routes to sublink0 */ 1241 1242 ASSERT((pDat->PortList[j].Link & 4) == (pDat->PortList[j+1].Link & 4)); /* (therefore sublink1 routes to sublink1) */ 1243 1243 1244 1244 if (pDat->HtBlock->AMD_CB_SkipRegang && 1245 1245 pDat->HtBlock->AMD_CB_SkipRegang(pDat->PortList[i].NodeID, 1246 1246 pDat->PortList[i].Link & 0x03, 1247 1247 pDat->PortList[i+1].NodeID, 1248 1248 pDat->PortList[i+1].Link & 0x03)) 1249 1249 { 1250 continue; / / Skip regang1251 } 1252 1253 1254 pDat->PortList[i].Link &= 0x03; / / Force to point to sublink01250 continue; /* Skip regang */ 1251 } 1252 1253 1254 pDat->PortList[i].Link &= 0x03; /* Force to point to sublink0 */ 1255 1255 pDat->PortList[i+1].Link &= 0x03; 1256 pDat->PortList[i].SelRegang = TRUE; / / Enable link reganging1256 pDat->PortList[i].SelRegang = TRUE; /* Enable link reganging */ 1257 1257 pDat->PortList[i+1].SelRegang = TRUE; 1258 1258 pDat->PortList[i].PrvWidthOutCap = HT_WIDTH_16_BITS; … … 1261 1261 pDat->PortList[i+1].PrvWidthInCap = HT_WIDTH_16_BITS; 1262 1262 1263 / / Delete PortList[j, j+1], slow but easy to debug implementation1263 /* Delete PortList[j, j+1], slow but easy to debug implementation */ 1264 1264 pDat->TotalLinks--; 1265 1265 Amdmemcpy(&(pDat->PortList[j]), &(pDat->PortList[j+2]), sizeof(sPortDescriptor)*(pDat->TotalLinks*2-j)); 1266 1266 Amdmemset(&(pDat->PortList[pDat->TotalLinks*2]), INVALID_LINK, sizeof(sPortDescriptor)*2); 1267 1267 1268 / ///High performance, but would make debuging harder due to 'shuffling' of the records1269 / ///Amdmemcpy(PortList[TotalPorts-2], PortList[j], SIZEOF(sPortDescriptor)*2);1270 / ///TotalPorts -=2;1271 1272 break; / / Exit loop, advance to PortList[i+2]1268 /* //High performance, but would make debuging harder due to 'shuffling' of the records */ 1269 /* //Amdmemcpy(PortList[TotalPorts-2], PortList[j], SIZEOF(sPortDescriptor)*2); */ 1270 /* //TotalPorts -=2; */ 1271 1272 break; /* Exit loop, advance to PortList[i+2] */ 1273 1273 } 1274 1274 } … … 1401 1401 for (i = 0; i < pDat->TotalLinks*2; i++) 1402 1402 { 1403 if (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) / / Must be a CPU link1403 if (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) /* Must be a CPU link */ 1404 1404 continue; 1405 if (pDat->PortList[i].Link < 4) / / Only look for for sublink1's1405 if (pDat->PortList[i].Link < 4) /* Only look for for sublink1's */ 1406 1406 continue; 1407 1407 1408 1408 for (j = 0; j < pDat->TotalLinks*2; j++) 1409 1409 { 1410 / / Step 1. Find the matching sublink01410 /* Step 1. Find the matching sublink0 */ 1411 1411 if (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) 1412 1412 continue; … … 1416 1416 continue; 1417 1417 1418 / / Step 2. Check for an illegal frequency ratio1418 /* Step 2. Check for an illegal frequency ratio */ 1419 1419 if (pDat->PortList[i].SelFrequency >= pDat->PortList[j].SelFrequency) 1420 1420 { … … 1431 1431 1432 1432 if (hiFreq == loFreq) 1433 break; / / The frequencies are 1:1, no need to do anything1433 break; /* The frequencies are 1:1, no need to do anything */ 1434 1434 1435 1435 downgrade = FALSE; … … 1437 1437 if (hiFreq == 13) 1438 1438 { 1439 if ((loFreq != 7) && / /{13, 7} 2400MHz / 1200MHz 2:11440 (loFreq != 4) && //{13, 4} 2400MHz / 600MHz 4:11441 (loFreq != 2) ) //{13, 2} 2400MHz / 400MHz 6:11439 if ((loFreq != 7) && /* {13, 7} 2400MHz / 1200MHz 2:1 */ 1440 (loFreq != 4) && /* {13, 4} 2400MHz / 600MHz 4:1 */ 1441 (loFreq != 2) ) /* {13, 2} 2400MHz / 400MHz 6:1 */ 1442 1442 downgrade = TRUE; 1443 1443 } 1444 1444 else if (hiFreq == 11) 1445 1445 { 1446 if ((loFreq != 6)) //{11, 6} 2000MHz / 1000MHz 2:11446 if ((loFreq != 6)) /* {11, 6} 2000MHz / 1000MHz 2:1 */ 1447 1447 downgrade = TRUE; 1448 1448 } 1449 1449 else if (hiFreq == 9) 1450 1450 { 1451 if ((loFreq != 5) && / /{ 9, 5} 1600MHz / 800MHz 2:11452 (loFreq != 2) && //{ 9, 2} 1600MHz / 400MHz 4:11453 (loFreq != 0) ) //{ 9, 0} 1600MHz / 200Mhz 8:11451 if ((loFreq != 5) && /* { 9, 5} 1600MHz / 800MHz 2:1 */ 1452 (loFreq != 2) && /* { 9, 2} 1600MHz / 400MHz 4:1 */ 1453 (loFreq != 0) ) /* { 9, 0} 1600MHz / 200Mhz 8:1 */ 1454 1454 downgrade = TRUE; 1455 1455 } 1456 1456 else if (hiFreq == 7) 1457 1457 { 1458 if ((loFreq != 4) && / /{ 7, 4} 1200MHz / 600MHz 2:11459 (loFreq != 0) ) //{ 7, 0} 1200MHz / 200MHz 6:11458 if ((loFreq != 4) && /* { 7, 4} 1200MHz / 600MHz 2:1 */ 1459 (loFreq != 0) ) /* { 7, 0} 1200MHz / 200MHz 6:1 */ 1460 1460 downgrade = TRUE; 1461 1461 } 1462 1462 else if (hiFreq == 5) 1463 1463 { 1464 if ((loFreq != 2) && / /{ 5, 2} 800MHz / 400MHz 2:11465 (loFreq != 0) ) //{ 5, 0} 800MHz / 200MHz 4:11464 if ((loFreq != 2) && /* { 5, 2} 800MHz / 400MHz 2:1 */ 1465 (loFreq != 0) ) /* { 5, 0} 800MHz / 200MHz 4:1 */ 1466 1466 downgrade = TRUE; 1467 1467 } 1468 1468 else if (hiFreq == 2) 1469 1469 { 1470 if ((loFreq != 0)) //{ 2, 0} 400MHz / 200MHz 2:11470 if ((loFreq != 0)) /* { 2, 0} 400MHz / 200MHz 2:1 */ 1471 1471 downgrade = TRUE; 1472 1472 } 1473 1473 else 1474 1474 { 1475 downgrade = TRUE; / / no legal ratios for hiFreq1476 } 1477 1478 / / Step 3. Downgrade the higher of the two frequencies, and set nochanges to FALSE1475 downgrade = TRUE; /* no legal ratios for hiFreq */ 1476 } 1477 1478 /* Step 3. Downgrade the higher of the two frequencies, and set nochanges to FALSE */ 1479 1479 if (downgrade) 1480 1480 { 1481 / / Although the problem was with the port specified by hiIndex, we need to1482 / / downgrade both ends of the link.1483 hiIndex = hiIndex & 0xFE; / / Select the 'upstream' (i.e. even) port1481 /* Although the problem was with the port specified by hiIndex, we need to */ 1482 /* downgrade both ends of the link. */ 1483 hiIndex = hiIndex & 0xFE; /* Select the 'upstream' (i.e. even) port */ 1484 1484 1485 1485 temp = pDat->PortList[hiIndex].CompositeFrequencyCap; 1486 1486 1487 / / Remove hiFreq from the list of valid frequencies1488 temp = temp & ~((u 32)1 << hiFreq);1487 /* Remove hiFreq from the list of valid frequencies */ 1488 temp = temp & ~((uint32)1 << hiFreq); 1489 1489 ASSERT (temp != 0); 1490 pDat->PortList[hiIndex].CompositeFrequencyCap = (u 16)temp;1491 pDat->PortList[hiIndex+1].CompositeFrequencyCap = (u 16)temp;1490 pDat->PortList[hiIndex].CompositeFrequencyCap = (uint16)temp; 1491 pDat->PortList[hiIndex+1].CompositeFrequencyCap = (uint16)temp; 1492 1492 1493 1493 for (k = 15; ; k--) … … 1504 1504 } 1505 1505 } 1506 } while (changes); / / Repeat until a valid configuration is reached1506 } while (changes); /* Repeat until a valid configuration is reached */ 1507 1507 #endif /* HT_BUILD_NC_ONLY */ 1508 1508 } … … 1551 1551 u8 i; 1552 1552 1553 / / Traffic Distribution is only used when there are exactly two nodes in the system1553 /* Traffic Distribution is only used when there are exactly two nodes in the system */ 1554 1554 if (pDat->NodesDiscovered+1 != 2) 1555 1555 return; … … 1569 1569 ASSERT(linkCount != 0); 1570 1570 if (linkCount == 1) 1571 return; / / Don't setup Traffic Distribution if only one link is being used1571 return; /* Don't setup Traffic Distribution if only one link is being used */ 1572 1572 1573 1573 pDat->nb->writeTrafficDistribution(links01, links10, pDat->nb); -
trunk/coreboot-v2/src/northbridge/amd/amdht/h3ncmn.c
r3052 r3423 334 334 linkBase = makeLinkBase(node, link); 335 335 336 / / FN0_98/A4/C4 = LDT Type Register336 /* FN0_98/A4/C4 = LDT Type Register */ 337 337 AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); 338 338 339 / / Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0339 /* Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ 340 340 return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT; 341 341 #else … … 1112 1112 return 2; 1113 1113 } 1114 STOP_HERE; / / This is an error internal condition1114 STOP_HERE; /* This is an error internal condition */ 1115 1115 1116 1116 return 0xFF; // make the compiler happy. 1117 1118 1117 } 1119 1118 … … 1144 1143 return 4; 1145 1144 } 1146 STOP_HERE; / / This is an internal error condition1145 STOP_HERE; /* This is an internal error condition */ 1147 1146 1148 1147 return 0xFF; // make the compiler happy. … … 1263 1262 AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG, 31, 16, &temp); 1264 1263 pDat->PortList[i].PrvFrequencyCap = (u16)temp & 0x7FFF 1265 & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); // Mask off bit 15, reserved value1264 & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); /* Mask off bit 15, reserved value */ 1266 1265 } 1267 1266 else … … 1385 1384 || (temp == HT_FREQUENCY_200M) || (temp == HT_FREQUENCY_400M)); 1386 1385 AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); 1387 if (temp > HT_FREQUENCY_1000M) / / Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz1386 if (temp > HT_FREQUENCY_1000M) /* Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz */ 1388 1387 { 1389 1388 /* Enable for Gen3 frequencies */
