Changeset 3418 for trunk/util/flashrom/spi.c
- Timestamp:
- 07/07/08 08:38:51 (5 months ago)
- Files:
-
- 1 modified
-
trunk/util/flashrom/spi.c (modified) (12 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/util/flashrom/spi.c
r3401 r3418 52 52 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID}; 53 53 54 if (spi_command( JEDEC_RDID_OUTSIZE, bytes, cmd, readarr))54 if (spi_command(sizeof(cmd), bytes, cmd, readarr)) 55 55 return 1; 56 56 printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]); … … 62 62 const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0}; 63 63 64 if (spi_command( JEDEC_RES_OUTSIZE, JEDEC_RES_INSIZE, cmd, readarr))64 if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr)) 65 65 return 1; 66 66 printf_debug("RES returned %02x.\n", readarr[0]); … … 73 73 74 74 /* Send WREN (Write Enable) */ 75 spi_command( JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL);75 spi_command(sizeof(cmd), 0, cmd, NULL); 76 76 } 77 77 … … 81 81 82 82 /* Send WRDI (Write Disable) */ 83 spi_command( JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL);83 spi_command(sizeof(cmd), 0, cmd, NULL); 84 84 } 85 85 … … 183 183 { 184 184 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR}; 185 unsigned char readarr[ 1];185 unsigned char readarr[JEDEC_RDSR_INSIZE]; 186 186 187 187 /* Read Status Register */ 188 spi_command( JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr);188 spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); 189 189 return readarr[0]; 190 190 } … … 274 274 spi_write_enable(); 275 275 /* Send CE (Chip Erase) */ 276 spi_command( JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL);276 spi_command(sizeof(cmd), 0, cmd, NULL); 277 277 /* Wait until the Write-In-Progress bit is cleared. 278 278 * This usually takes 1-85 s, so wait in 1 s steps. … … 297 297 spi_write_enable(); 298 298 /* Send BE (Block Erase) */ 299 spi_command( JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL);299 spi_command(sizeof(cmd), 0, cmd, NULL); 300 300 /* Wait until the Write-In-Progress bit is cleared. 301 301 * This usually takes 100-4000 ms, so wait in 100 ms steps. … … 316 316 spi_write_enable(); 317 317 /* Send SE (Sector Erase) */ 318 spi_command( JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL);318 spi_command(sizeof(cmd), 0, cmd, NULL); 319 319 /* Wait until the Write-In-Progress bit is cleared. 320 320 * This usually takes 15-800 ms, so wait in 10 ms steps. … … 325 325 } 326 326 327 void spi_page_program(int block, uint8_t *buf, uint8_t *bios)328 {329 switch (flashbus) {330 case BUS_TYPE_IT87XX_SPI:331 it8716f_spi_page_program(block, buf, bios);332 break;333 case BUS_TYPE_ICH7_SPI:334 case BUS_TYPE_ICH9_SPI:335 printf_debug("%s called, but not implemented for ICH\n", __FUNCTION__);336 break;337 default:338 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);339 }340 }341 342 327 /* 343 328 * This is according the SST25VF016 datasheet, who knows it is more … … 349 334 350 335 /* Send WRSR (Write Status Register) */ 351 spi_command( JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL);336 spi_command(sizeof(cmd), 0, cmd, NULL); 352 337 } 353 338 … … 362 347 363 348 /* Send Byte-Program */ 364 spi_command( JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL);349 spi_command(sizeof(cmd), 0, cmd, NULL); 365 350 } 366 351 … … 387 372 388 373 /* Send Read */ 389 spi_command( JEDEC_READ_OUTSIZE, len, cmd, bytes);374 spi_command(sizeof(cmd), len, cmd, bytes); 390 375 } 391 376
