| 44 | | #define TLB_SIZE 1024 |
| | 43 | #define TLB_SIZE 1024 |
| | 44 | |
| | 45 | /*----------------------------------------------------------------------------+ |
| | 46 | | Partial memory map. |
| | 47 | +----------------------------------------------------------------------------*/ |
| | 48 | #define SDRAM_BASE 0x0000000000000000UL |
| | 49 | #define SDRAM_SIZE 0x0000000080000000UL |
| | 50 | #define IO_BASE 0x0000000080000000UL |
| | 51 | #define IO_SIZE 0x0000000080000000UL |
| | 52 | #define PCI_BUS_MEM_BASE 0x0000000080000000UL |
| | 53 | #define PCI_BUS_MEM_SIZE 0x0000000070000000UL |
| | 54 | #define PCI0_BASE 0x00000000F0000000UL |
| | 55 | #define PCI0_SIZE 0x0000000002000000UL |
| | 56 | #define HT1_BASE 0x00000000F2000000UL |
| | 57 | #define HT1_SIZE 0x0000000003000000UL |
| | 58 | #define PPC925_BASE 0x00000000F8000000UL |
| | 59 | #define PPC925_SIZE 0x0000000001000000UL |
| | 60 | #define SB_IOAPIC_BASE 0x00000000FEC00000UL |
| | 61 | #define BOOT_BASE 0x00000000FF000000UL |
| | 62 | #define BOOT_BASE_AS 0x00000000FF000000 |
| | 63 | #define BOOT_END 0x00000000FFFFFFFFUL |
| | 64 | #define FLASH_BASE_INTEL 0x00000000FF800000UL |
| | 65 | #define FLASH_BASE_INTEL_AS 0x00000000FF800000 |
| | 66 | #define FLASH_BASE_AMD 0x00000000FFF00000UL |
| | 67 | #define FLASH_BASE_AMD_AS 0x00000000FFF00000 |
| | 68 | #define SDRAM_UPPER_BASE 0x0000000100000000UL |
| | 69 | #define SDRAM_UPPER_SIZE 0x0000000F00000000UL |
| | 70 | |
| | 71 | /*----------------------------------------------------------------------------+ |
| | 72 | | BOOT_STACK_ADDR is data used for stack before SDRAM is available. This data |
| | 73 | | will be written to memory after the SDRAM is initialized. All values here |
| | 74 | | must be less than 32 bits. Following 13 defines need to be changed when |
| | 75 | | changing the location of PIBS in SDRAM (the link file also need to be |
| | 76 | | changed in order to fully relocate PIBS. |
| | 77 | +----------------------------------------------------------------------------*/ |
| | 78 | #define PIBS_BASE_ADDR 0x00C00000 |
| | 79 | #define BOOT_STACK_ADDR 0x00C50000 |
| | 80 | #define BOOT_STACK_SIZE 0x00004000 |
| | 81 | #define MEM_CHK_START_ADDR 0x00C40000 |
| | 82 | #define MEM_CHK_SIZE 0x00010000 |
| | 83 | |
| | 84 | /*----------------------------------------------------------------------------+ |
| | 85 | | Address of a CPU0, CPU1 shared memory structure. |
| | 86 | +----------------------------------------------------------------------------*/ |
| | 87 | #define CPU1_DATA_STRUCT_ADDR 0x00C00040 |
| | 88 | #define CPU1_DATA_STRUCT_SRR0_OFF 0x00000000 |
| | 89 | #define CPU1_DATA_STRUCT_SRR1_OFF 0x00000008 |
| | 90 | #define CPU1_DATA_STRUCT_R3_OFF 0x00000010 |
| | 91 | #define CPU1_DATA_STRUCT_VALID_OFF 0x00000018 |
| | 92 | |
| | 93 | /*----------------------------------------------------------------------------+ |
| | 94 | | Address of the memory location used for the test and set instruction |
| | 95 | | sequence. |
| | 96 | +----------------------------------------------------------------------------*/ |
| | 97 | #define VM_TEST_AND_SET_ADDR 0x0000000000C000F0UL |
| | 98 | |
| | 99 | /*----------------------------------------------------------------------------+ |
| | 100 | | Initial page table address. |
| | 101 | +----------------------------------------------------------------------------*/ |
| | 102 | #define INITIAL_PAGE_TABLE_ADDR_CPU0 0x0000000000D00000 |
| | 103 | #define INITIAL_PAGE_TABLE_ADDR_CPU1 0x0000000000D40000 |
| | 104 | #define INITIAL_PAGE_TABLE_SIZE 0x0000000000040000 |
| | 105 | |
| | 106 | /*----------------------------------------------------------------------------+ |
| | 107 | | Initial stack size. Must be less than 32 bits in length. |
| | 108 | +----------------------------------------------------------------------------*/ |
| | 109 | #define MY_MAIN_STACK_SIZE (8* 1024) |
| | 110 | |
| | 111 | /*----------------------------------------------------------------------------+ |
| | 112 | | Serial port address. The base address must be programmed into super I/O. The |
| | 113 | | external time base is available only on JS20. |
| | 114 | +----------------------------------------------------------------------------*/ |
| | 115 | #define UART1_MMIO_BASE 0xF40002F8UL |
| | 116 | #define UART0_MMIO_BASE 0xF40003F8UL |
| | 117 | #define UART1_MMIO_OFFSET 0x2F8; |
| | 118 | #define UART0_MMIO_OFFSET 0x3F8; |
| | 119 | #define UART_INPUT_CLOCK 1843200 |
| | 120 | #define EXT_TIME_BASE_FREQ 0 |
| | 121 | #define DIV_HIGH_9600 0x00 |
| | 122 | #define DIV_LOW_9600 0x0C |
| | 123 | |
| | 124 | #define EXT_IRQ_COM1 EXT_SB_HT4 |
| | 125 | #define EXT_IRQ_COM2 EXT_SB_HT3 |
| | 126 | |
| | 127 | /*----------------------------------------------------------------------------+ |
| | 128 | | Locations in Super I/O NVRAM where service processor stores information for |
| | 129 | | the PPC970FX CPU. |
| | 130 | +----------------------------------------------------------------------------*/ |
| | 131 | #define SUPER_IO_NVRAM_DATA_VALID 64 |
| | 132 | #define SUPER_IO_NVRAM_SYS_CLK (SUPER_IO_NVRAM_DATA_VALID+ 0x04) |
| | 133 | #define SUPER_IO_NVRAM_CLK_MULT (SUPER_IO_NVRAM_SYS_CLK+ 0x04) |
| | 134 | #define SUPER_IO_NVRAM_EI_RATIO (SUPER_IO_NVRAM_CLK_MULT+ 0x01) |
| | 135 | |
| | 136 | #define SUPER_IO_VALID_VALUE 0x426F4F6D |
| | 137 | |
| | 138 | #define PPC970_EI_RATIO_000 2 |
| | 139 | #define PPC970_EI_RATIO_001 3 |
| | 140 | #define PPC970_EI_RATIO_010 4 |
| | 141 | #define PPC970_EI_RATIO_011 6 |
| | 142 | #define PPC970_EI_RATIO_100 8 |
| | 143 | #define PPC970_EI_RATIO_101 12 |
| | 144 | #define PPC970_EI_RATIO_110 16 |
| | 145 | |
| | 146 | /*----------------------------------------------------------------------------+ |
| | 147 | | Locations in Super I/O NVRAM where PPC970 store commands for service |
| | 148 | | processor. 0x01 is written by PPC970 to initiate action by the service |
| | 149 | | processor. This value is cleared by the service processor upon receiving |
| | 150 | | the command. |
| | 151 | +----------------------------------------------------------------------------*/ |
| | 152 | #define SUPER_IO_NVRAM_POWER_OFF 96 |
| | 153 | #define SUPER_IO_NVRAM_RESTART (SUPER_IO_NVRAM_POWER_OFF+ 0x2) |
| | 154 | |
| | 155 | /*----------------------------------------------------------------------------+ |
| | 156 | | Default HID register settings. |
| | 157 | +----------------------------------------------------------------------------*/ |
| | 158 | #define HID0_PREFEAR 0x0011008180000000 |
| | 159 | #define HID1_PREFEAR 0xFD3C200000000000 |
| | 160 | #define HID4_PREFEAR 0x0000001000000000 |
| | 161 | #define HID5_PREFEAR 0x0000000000000080 |
| | 162 | |
| | 163 | /*----------------------------------------------------------------------------+ |
| | 164 | | Power control SCOM register definitions. |
| | 165 | +----------------------------------------------------------------------------*/ |
| | 166 | #define SCOM_ADDR_PCR_WRITE 0x000000000AA00000UL |
| | 167 | #define SCOM_ADDR_PCR_WRITE_ASM 0x000000000AA00000 |
| | 168 | #define SCOM_ADDR_PSR_READ 0x0000000040808000UL |
| | 169 | #define SCOM_ADDR_PSR_READ_ASM 0x0000000040808000 |
| | 170 | |
| | 171 | #define SCOM_ADDR_PCR_DATA_MASK 0x0000000080000000UL |
| | 172 | #define SCOM_ADDR_PCR_DATA_MASK_ASM 0x0000000080000000 |
| | 173 | |
| | 174 | #define SCOM_ADDR_PCR_FREQ_VALID 0x0000000000010000UL |
| | 175 | #define SCOM_ADDR_PCR_FREQ_FULL 0x0000000000000000UL |
| | 176 | #define SCOM_ADDR_PCR_FREQ_HALF 0x0000000000020000UL |
| | 177 | #define SCOM_ADDR_PCR_FREQ_QUARTER 0x0000000000040000UL |
| | 178 | |
| | 179 | #define SCOM_PSR_FREQ_MASK 0x0300000000000000UL |
| | 180 | #define SCOM_PSR_FREQ_FULL 0x0000000000000000UL |
| | 181 | #define SCOM_PSR_FREQ_HALF 0x0100000000000000UL |
| | 182 | #define SCOM_PSR_FREQ_QUARTER 0x0200000000000000UL |
| | 183 | #define SCOM_PSR_COMM_COMPLETED 0x1000000000000000UL |
| | 184 | #define SCOM_PSR_COMM_COMPLETED_ASM 0x1000000000000000 |
| | 185 | |
| | 186 | /*----------------------------------------------------------------------------+ |
| | 187 | | Serial port for CPU2 |
| | 188 | +----------------------------------------------------------------------------*/ |
| | 189 | #define CPU2_SERIAL_PORT 2 |
| | 190 | #define CPU2_BAUD_RATE 115200 |
| | 191 | |
| | 192 | /*----------------------------------------------------------------------------+ |
| | 193 | | External interrupt assignments. |
| | 194 | +----------------------------------------------------------------------------*/ |
| | 195 | #define EXT_I2C_MASTER 0 |
| | 196 | #define EXT_VSP 1 |
| | 197 | #define EXT_HT1_BRIDGE 2 |
| | 198 | #define EXT_PCI0_AGP_BRIDGE 3 |
| | 199 | #define EXT_SLEEP0 4 |
| | 200 | #define EXT_SLEEP1 5 |
| | 201 | #define EXT_SB_HT0 6 |
| | 202 | #define EXT_SB_HT1 7 |
| | 203 | #define EXT_SB_HT2 8 |
| | 204 | #define EXT_SB_HT3 9 |
| | 205 | #define EXT_SB_HT4 10 |
| | 206 | #define EXT_SB_HT5 11 |
| | 207 | #define EXT_SB_HT6 12 |
| | 208 | #define EXT_SB_HT7 13 |
| | 209 | #define EXT_SB_HT8 14 |
| | 210 | #define EXT_SB_HT9 15 |
| | 211 | #define EXT_SB_HT10 16 |
| | 212 | #define EXT_SB_HT11 17 |
| | 213 | #define EXT_SB_HT12 18 |
| | 214 | #define EXT_SB_HT13 19 |
| | 215 | #define EXT_SB_HT14 20 |
| | 216 | #define EXT_SB_HT15 21 |
| | 217 | #define EXT_SB_HT16 22 |
| | 218 | #define EXT_SB_HT17 23 |
| | 219 | #define EXT_SB_HT18 24 |
| | 220 | #define EXT_SB_HT19 25 |
| | 221 | #define EXT_SB_HT20 26 |
| | 222 | #define EXT_SB_HT21 27 |
| | 223 | #define EXT_SB_HT22 28 |
| | 224 | #define EXT_SB_HT23 29 |
| | 225 | #define EXT_SB_HT24 30 |
| | 226 | #define EXT_SB_HT25 31 |
| | 227 | #define EXT_SB_HT26 32 |
| | 228 | #define EXT_SB_HT27 33 |
| | 229 | #define EXT_SB_HT28 34 |
| | 230 | #define EXT_SB_HT29 35 |
| | 231 | #define EXT_SB_HT30 36 |
| | 232 | #define EXT_SB_HT31 37 |
| | 233 | #define EXT_SB_HT32 38 |
| | 234 | #define EXT_SB_HT33 39 |
| | 235 | #define EXT_SB_HT34 40 |
| | 236 | #define EXT_SB_HT35 41 |
| | 237 | #define EXT_SB_HT36 42 |
| | 238 | #define EXT_SB_HT37 43 |
| | 239 | #define EXT_SB_HT38 44 |
| | 240 | #define EXT_SB_HT39 45 |
| | 241 | #define EXT_SB_HT40 46 |
| | 242 | #define EXT_SB_HT41 47 |
| | 243 | #define EXT_SB_HT42 48 |
| | 244 | #define EXT_SB_HT43 49 |
| | 245 | #define EXT_SB_HT44 50 |
| | 246 | #define EXT_SB_HT45 51 |
| | 247 | #define EXT_SB_HT46 52 |
| | 248 | #define EXT_SB_HT47 53 |
| | 249 | #define EXT_SB_HT48 54 |
| | 250 | #define EXT_SB_HT49 55 |
| | 251 | #define EXT_SB_HT50 56 |
| | 252 | #define EXT_SB_HT51 57 |
| | 253 | #define EXT_SB_HT52 58 |
| | 254 | #define EXT_SB_HT53 59 |
| | 255 | #define EXT_SB_HT54 60 |
| | 256 | #define EXT_SB_HT55 61 |
| | 257 | #define EXT_SB_HT56 62 |
| | 258 | #define EXT_SB_HT57 63 |
| | 259 | #define EXT_SB_HT58 64 |
| | 260 | #define EXT_SB_HT59 65 |
| | 261 | #define EXT_SB_HT60 66 |
| | 262 | #define EXT_SB_HT61 67 |
| | 263 | #define EXT_SB_HT62 68 |
| | 264 | #define EXT_SB_HT63 69 |
| | 265 | #define EXT_SB_HT64 70 |
| | 266 | #define EXT_SB_HT65 71 |
| | 267 | #define EXT_SB_HT66 72 |
| | 268 | #define EXT_SB_HT67 73 |
| | 269 | #define EXT_SB_HT68 74 |
| | 270 | #define EXT_SB_HT69 75 |
| | 271 | #define EXT_SB_HT70 76 |
| | 272 | #define EXT_SB_HT71 77 |
| | 273 | #define EXT_SB_HT72 78 |
| | 274 | #define EXT_SB_HT73 79 |
| | 275 | #define EXT_SB_HT74 80 |
| | 276 | #define EXT_SB_HT75 81 |
| | 277 | #define EXT_SB_HT76 82 |
| | 278 | #define EXT_SB_HT77 83 |
| | 279 | #define EXT_SB_HT78 84 |
| | 280 | #define EXT_SB_HT79 85 |
| | 281 | #define EXT_SB_HT80 86 |
| | 282 | #define EXT_SB_HT81 87 |
| | 283 | #define EXT_SB_HT82 88 |
| | 284 | #define EXT_SB_HT83 89 |
| | 285 | #define EXT_SB_HT84 90 |
| | 286 | #define EXT_SB_HT85 91 |
| | 287 | #define EXT_SB_HT86 92 |
| | 288 | #define EXT_SB_HT87 93 |
| | 289 | #define EXT_SB_HT88 94 |
| | 290 | #define EXT_SB_HT90 95 |
| | 291 | #define EXT_SB_HT91 96 |
| | 292 | #define EXT_SB_HT92 97 |
| | 293 | #define EXT_SB_HT93 98 |
| | 294 | #define EXT_SB_HT94 99 |
| | 295 | #define EXT_SB_HT95 100 |
| | 296 | #define EXT_SB_HT96 101 |
| | 297 | #define EXT_SB_HT97 102 |
| | 298 | #define EXT_SB_HT98 103 |
| | 299 | #define EXT_SB_HT99 104 |
| | 300 | #define EXT_SB_HT100 105 |
| | 301 | #define EXT_SB_HT101 106 |
| | 302 | #define EXT_SB_HT102 107 |
| | 303 | #define EXT_SB_HT103 108 |
| | 304 | #define EXT_SB_HT104 109 |
| | 305 | #define EXT_SB_HT105 110 |
| | 306 | #define EXT_SB_HT106 111 |
| | 307 | #define EXT_SB_HT107 112 |
| | 308 | #define EXT_SB_HT108 113 |
| | 309 | #define EXT_SB_HT109 114 |
| | 310 | #define EXT_SB_HT110 115 |
| | 311 | #define EXT_SB_HT111 116 |
| | 312 | #define EXT_SB_HT112 117 |
| | 313 | #define EXT_SB_HT113 118 |
| | 314 | #define EXT_SB_HT114 119 |
| | 315 | #define EXT_SB_HT115 120 |
| | 316 | #define EXT_SB_HT116 121 |
| | 317 | #define EXT_SB_HT117 122 |
| | 318 | #define EXT_SB_HT118 123 |
| | 319 | #define EXT_IPI_0 124 |
| | 320 | #define EXT_IPI_1 125 |
| | 321 | #define EXT_MAX_IRQ_NUM 125 |
| | 322 | |
| | 323 | /*----------------------------------------------------------------------------+ |
| | 324 | | # # # ###### ####### |
| | 325 | | # # # # # # # |
| | 326 | | # # # # # # # |
| | 327 | | # # # # ###### # |
| | 328 | | # # ####### # # # |
| | 329 | | # # # # # # # |
| | 330 | | ##### # # # # # |
| | 331 | +----------------------------------------------------------------------------*/ |
| | 332 | |
| | 333 | /*----------------------------------------------------------------------------+ |
| | 334 | | Interrupt Enable Register. DLAB must be set to 0 access this register. |
| | 335 | +----------------------------------------------------------------------------*/ |
| | 336 | #define asyncIER 1 |
| | 337 | #define asyncIERModem 0x08 |
| | 338 | #define asyncIERLine 0x04 |
| | 339 | #define asyncIERTransmit 0x02 |
| | 340 | #define asyncIERReceive 0x01 |
| | 341 | #define asyncIERdisableAll 0x00 |
| | 342 | |
| | 343 | /*----------------------------------------------------------------------------+ |
| | 344 | | Interrupt Identification Register. Read only register. |
| | 345 | +----------------------------------------------------------------------------*/ |
| | 346 | #define asyncIIR 2 |
| | 347 | #define asyncIIRMask 0x0F |
| | 348 | #define asyncIIRFifoTimeout 0x0C |
| | 349 | #define asyncIIRLine 0x06 |
| | 350 | #define asyncIIRReceive 0x04 |
| | 351 | #define asyncIIRTransmit 0x02 |
| | 352 | #define asyncIIRNoInterrupt 0x01 |
| | 353 | #define asyncIIRModem 0x00 |
| | 354 | |
| | 355 | /*----------------------------------------------------------------------------+ |
| | 356 | | FIFO Control Register. Write only register. |
| | 357 | +----------------------------------------------------------------------------*/ |
| | 358 | #define asyncFCR 2 |
| | 359 | #define asyncFCRFifoTrigger14 0xC0 |
| | 360 | #define asyncFCRFifoTrigger8 0x80 |
| | 361 | #define asyncFCRFifoTrigger4 0x40 |
| | 362 | #define asyncFCRFifoTrigger1 0x00 |
| | 363 | #define asyncFCRDmaSet 0x08 |
| | 364 | #define asyncFCRClearXmitFifo 0x04 |
| | 365 | #define asyncFCRClearRcvFifo 0x02 |
| | 366 | #define asyncFCRFifoEnable 0x01 |
| | 367 | |
| | 368 | /*----------------------------------------------------------------------------+ |
| | 369 | | Line Control Register. |
| | 370 | +----------------------------------------------------------------------------*/ |
| | 371 | #define asyncLCR 3 |
| | 372 | #define asyncLCRDLAB 0x80 |
| | 373 | #define asyncLCRSetBreak 0x40 |
| | 374 | #define asyncLCRStickParity 0x20 |
| | 375 | #define asyncLCREvenParity 0x10 |
| | 376 | #define asyncLCROddParity 0x00 |
| | 377 | #define asyncLCRParityEnable 0x08 |
| | 378 | #define asyncLCRParityDisable 0x00 |
| | 379 | #define asyncLCRStopBitsTwo 0x04 |
| | 380 | #define asyncLCRStopBitsOne 0x00 |
| | 381 | #define asyncLCRWordLengthSel 0x03 |
| | 382 | #define asyncLCRWordLength5 0x00 |
| | 383 | #define asyncLCRWordLength6 0x01 |
| | 384 | #define asyncLCRWordLength7 0x02 |
| | 385 | #define asyncLCRWordLength8 0x03 |
| | 386 | |
| | 387 | /*----------------------------------------------------------------------------+ |
| | 388 | | Modem Control Register. |
| | 389 | +----------------------------------------------------------------------------*/ |
| | 390 | #define asyncMCR 4 |
| | 391 | #define asyncMCRLoop 0x10 |
| | 392 | #define asyncMCROut2 0x08 |
| | 393 | #define asyncMCROut1 0x04 |
| | 394 | #define asyncMCRRTS 0x02 |
| | 395 | #define asyncMCRDTR 0x01 |
| | 396 | #define asyncMCRdisableAll 0x00 |
| | 397 | |
| | 398 | /*----------------------------------------------------------------------------+ |
| | 399 | | Line Status Register. |
| | 400 | +----------------------------------------------------------------------------*/ |
| | 401 | #define asyncLSR 5 |
| | 402 | #define asyncLSRRxFifoError 0x80 |
| | 403 | #define asyncLSRTxEmpty 0x60 |
| | 404 | #define asyncLSRTxShiftEmpty 0x40 |
| | 405 | #define asyncLSRTxHoldEmpty 0x20 |
| | 406 | #define asyncLSRBreakInterrupt 0x10 |
| | 407 | #define asyncLSRFramingError 0x08 |
| | 408 | #define asyncLSRParityError 0x04 |
| | 409 | #define asyncLSROverrunError 0x02 |
| | 410 | #define asyncLSRDataReady 0x01 |
| | 411 | |
| | 412 | /*----------------------------------------------------------------------------+ |
| | 413 | | Modem Status Register. Read only register. |
| | 414 | +----------------------------------------------------------------------------*/ |
| | 415 | #define asyncMSR 6 |
| | 416 | #define asyncMSRCD 0x80 |
| | 417 | #define asyncMSRRI 0x40 |
| | 418 | #define asyncMSRDSR 0x20 |
| | 419 | #define asyncMSRCTS 0x10 |
| | 420 | #define asyncMSRDeltaDCD 0x08 |
| | 421 | #define asyncMSRDeltaRI 0x04 |
| | 422 | #define asyncMSRDeltaDSR 0x02 |
| | 423 | #define asyncMSRDeltaCTS 0x01 |
| | 424 | |
| | 425 | /*----------------------------------------------------------------------------+ |
| | 426 | | Miscellanies defines. |
| | 427 | +----------------------------------------------------------------------------*/ |
| | 428 | #define asyncScratchReg 7 |
| | 429 | #define asyncTxBuffer 0 |
| | 430 | #define asyncRxBuffer 0 |
| | 431 | #define asyncDLABLsb 0 |
| | 432 | #define asyncDLABMsb 1 |
| | 433 | |
| | 434 | /*----------------------------------------------------------------------------+ |
| | 435 | | ##### ###### ##### ##### ##### ####### |
| | 436 | | # # # # # # # # # # # |
| | 437 | | # # # # # # # # |
| | 438 | | # ###### # ###### ##### ###### |
| | 439 | | # # # # # # |
| | 440 | | # # # # # # # # # # |
| | 441 | | ##### # ##### ##### ####### ##### |
| | 442 | +----------------------------------------------------------------------------*/ |
| | 443 | |
| | 444 | /*----------------------------------------------------------------------------+ |
| | 445 | | When performing PCI configuration read/write the configuration address |
| | 446 | | register must be written and then read before configuration data register is |
| | 447 | | accessed. |
| | 448 | | PCI type 0 Configuration address format is: |
| | 449 | | 0-20 id. sel., 21-23 function number, 24-29 register number|00 |
| | 450 | +----------------------------------------------------------------------------*/ |
| | 451 | #define NB_PCI_CONFIGURATION_ADDR 0x0F0800000UL |
| | 452 | #define NB_PCI_CONFIGURATION_DATA 0x0F0C00000UL |
| | 453 | |
| | 454 | /*----------------------------------------------------------------------------+ |
| | 455 | | When performing HT configuration read/write the configuration address |
| | 456 | | register must be written and then read before configuration data register is |
| | 457 | | accessed. |
| | 458 | | HT type 0 Configuration address format is: |
| | 459 | | 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|00 |
| | 460 | | HT type 1 configuration address format is |
| | 461 | | 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|01 |
| | 462 | +----------------------------------------------------------------------------*/ |
| | 463 | #define NB_HT_CONFIGURATION_ADDR 0x0F2800000UL |
| | 464 | #define NB_HT_CONFIGURATION_DATA 0x0F2C00000UL |
| | 465 | |
| | 466 | /*----------------------------------------------------------------------------+ |
| | 467 | | HT Configuration Address Spaces. |
| | 468 | +----------------------------------------------------------------------------*/ |
| | 469 | #define NB_HT_CONFIG_TYPE_0_BASE 0x0F2000000UL |
| | 470 | #define NB_HT_CONFIG_TYPE_1_BASE 0x0F3000000UL |
| | 471 | |
| | 472 | /*----------------------------------------------------------------------------+ |
| | 473 | | HT I/O Space. NB_HT_IO_RESERVED is reserved for Super I/O peripherals. The |
| | 474 | | SuperI/O utilizes subtractive decode. All PCI I/0 addresses are translated |
| | 475 | | from 0xF4xxxxxx (CPU) to 0x00xxxxxx (PCI). |
| | 476 | +----------------------------------------------------------------------------*/ |
| | 477 | #define NB_HT_IO_BASE_CPU 0x0F4000000UL |
| | 478 | #define NB_HT_IO_BASE_BYTE 0xF4 |
| | 479 | #define NB_HT_IO_BASE_BYTE_SH 24 |
| | 480 | #define NB_HT_IO_BASE_PCI 0x000000000UL |
| | 481 | #define NB_HT_IO_BASE_ASM 0xF4000000 |
| | 482 | #define NB_HT_IO_SIZE 0x000400000UL |
| | 483 | #define NB_HT_IO_RESERVED 0x000010000UL |
| | 484 | |
| | 485 | /*----------------------------------------------------------------------------+ |
| | 486 | | HT EOI Space. |
| | 487 | +----------------------------------------------------------------------------*/ |
| | 488 | #define NB_HT_EOI_BASE 0x0F4400000UL |
| | 489 | #define NB_HT_EOI_SIZE 0x000400000UL |
| | 490 | |
| | 491 | /*----------------------------------------------------------------------------+ |
| | 492 | | HT Device Header Regs. Big Endian. |
| | 493 | +----------------------------------------------------------------------------*/ |
| | 494 | #define NB_HT_REG_BASE 0x0F8070000UL |
| | 495 | #define NB_HT_DID_VID 0x0F8070000UL |
| | 496 | #define NB_HT_STAT_CMD 0x0F8070010UL |
| | 497 | #define NB_HT_CLASS_REV 0x0F8070020UL |
| | 498 | #define NB_HT_BIST_HT 0x0F8070030UL |
| | 499 | #define NB_HT_CAP_PTR 0x0F80700D0UL |
| | 500 | #define NB_HT_INT_LINE 0x0F80700F0UL |
| | 501 | |
| | 502 | /*----------------------------------------------------------------------------+ |
| | 503 | | HT Capabilities Block. Big Endian. |
| | 504 | +----------------------------------------------------------------------------*/ |
| | 505 | #define NB_HT_CMD_PTR_ID 0x0F8070100UL |
| | 506 | #define HT_WARM_RESET 0x00010000 |
| | 507 | #define NB_HT_LINK_CFG_CONTROL 0x0F8070110UL |
| | 508 | #define HT_CRC_ERR 0x00000F00 |
| | 509 | #define HT_END_OF_CHAIN 0x00000040 |
| | 510 | #define HT_INIT 0x00000020 |
| | 511 | #define HT_LINK_FAIL 0x00000010 |
| | 512 | #define HT_LINK_OUT_MASK 0x70000000 |
| | 513 | #define HT_LINK_IN_MASK 0x07000000 |
| | 514 | #define HT_LINK_MAX_OUT_MASK 0x00700000 |
| | 515 | #define HT_LINK_MAX_IN_MASK 0x00070000 |
| | 516 | #define HT_LINK_WIDTH_8_BIT 0x0 |
| | 517 | #define HT_LINK_WIDTH_16_BIT 0x1 |
| | 518 | #define HT_LINK_WIDTH_32_BIT 0x3 |
| | 519 | #define HT_LINK_WIDTH_2_BIT 0x4 |
| | 520 | #define HT_LINK_WIDTH_4_BIT 0x5 |
| | 521 | #define NB_HT_LINK_FREQ_ERROR 0x0F8070120UL |
| | 522 | #define HT_LINK_FREQ_CAP_MASK 0xFFFF0000 |
| | 523 | #define HT_LINK_FREQ_MASK 0x00000F00 |
| | 524 | #define HT_LINK_FREQ_200 0x0 |
| | 525 | #define HT_LINK_FREQ_300 0x1 |
| | 526 | #define HT_LINK_FREQ_400 0x2 |
| | 527 | #define HT_LINK_FREQ_500 0x3 |
| | 528 | #define HT_LINK_FREQ_600 0x4 |
| | 529 | #define HT_LINK_FREQ_800 0x5 |
| | 530 | #define HT_LINK_FREQ_1000 0x6 |
| | 531 | |
| | 532 | /*----------------------------------------------------------------------------+ < |
