source: trunk/src/northbridge/intel/i945/northbridge.c @ 5937

Last change on this file since 5937 was 5937, checked in by uwe, 5 years ago

Factor out a few commonly duplicated functions from northbridge.c.

The following functions are moved to devices/device_util.c:

  • ram_resource()
  • tolm_test()
  • find_pci_tolm()

There are only two tolm_test() / find_pci_tolm() which differ from the
defaults, one of them can easily be eliminated in a follow-up patch,
maybe even both, but for now keep it simple and only eliminate the majority.

Signed-off-by: Uwe Hermann <uwe@…>
Acked-by: Peter Stuge <peter@…>

File size: 8.6 KB
Line 
1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
18 */
19
20#include <console/console.h>
21#include <arch/io.h>
22#include <stdint.h>
23#include <device/device.h>
24#include <device/pci.h>
25#include <device/pci_ids.h>
26#include <device/hypertransport.h>
27#include <stdlib.h>
28#include <string.h>
29#include <bitops.h>
30#include <cpu/cpu.h>
31#include <boot/tables.h>
32#include "chip.h"
33#include "i945.h"
34
35static int get_pcie_bar(u32 *base, u32 *len)
36{
37        device_t dev;
38        u32 pciexbar_reg;
39
40        *base = 0;
41        *len = 0;
42
43        dev = dev_find_slot(0, PCI_DEVFN(0, 0));
44        if (!dev)
45                return 0;
46
47        pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
48
49        if (!(pciexbar_reg & (1 << 0)))
50                return 0;
51
52        switch ((pciexbar_reg >> 1) & 3) {
53        case 0: // 256MB
54                *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
55                *len = 256 * 1024 * 1024;
56                return 1;
57        case 1: // 128M
58                *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
59                *len = 128 * 1024 * 1024;
60                return 1;
61        case 2: // 64M
62                *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
63                *len = 64 * 1024 * 1024;
64                return 1;
65        }
66
67        return 0;
68}
69
70/* IDG memory */
71uint64_t uma_memory_base=0, uma_memory_size=0;
72
73static void add_fixed_resources(struct device *dev, int index)
74{
75        struct resource *resource;
76        u32 pcie_config_base, pcie_config_size;
77
78        printk(BIOS_DEBUG, "Adding UMA memory area\n");
79        resource = new_resource(dev, index);
80        resource->base = (resource_t) uma_memory_base;
81        resource->size = (resource_t) uma_memory_size;
82        resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
83            IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
84
85        if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
86                printk(BIOS_DEBUG, "Adding PCIe config bar\n");
87                resource = new_resource(dev, index+1);
88                resource->base = (resource_t) pcie_config_base;
89                resource->size = (resource_t) pcie_config_size;
90                resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
91                    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
92        }
93}
94
95#if CONFIG_WRITE_HIGH_TABLES==1
96#define HIGH_TABLES_SIZE 1024   // maximum size of high tables in KB
97extern uint64_t high_tables_base, high_tables_size;
98#endif
99
100static void pci_domain_set_resources(device_t dev)
101{
102        uint32_t pci_tolm;
103        uint8_t tolud, reg8;
104        uint16_t reg16;
105        unsigned long long tomk;
106
107        /* Can we find out how much memory we can use at most
108         * this way?
109         */
110        pci_tolm = find_pci_tolm(dev->link_list);
111        printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
112
113        printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
114                    pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
115
116        tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
117        printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
118
119        tomk = tolud << 14;
120
121        /* Note: subtract IGD device and TSEG */
122        reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
123        if (reg8 & 1) {
124                int tseg_size = 0;
125                printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
126                reg8 >>= 1;
127                reg8 &= 3;
128                switch (reg8) {
129                case 0:
130                        tseg_size = 1024;
131                        break;  /* TSEG = 1M */
132                case 1:
133                        tseg_size = 2048;
134                        break;  /* TSEG = 2M */
135                case 2:
136                        tseg_size = 8192;
137                        break;  /* TSEG = 8M */
138                }
139
140                printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
141                tomk -= tseg_size;
142        }
143
144        reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
145        if (!(reg16 & 2)) {
146                int uma_size = 0;
147                printk(BIOS_DEBUG, "IGD decoded, subtracting ");
148                reg16 >>= 4;
149                reg16 &= 7;
150                switch (reg16) {
151                case 1:
152                        uma_size = 1024;
153                        break;
154                case 3:
155                        uma_size = 8192;
156                        break;
157                }
158
159                printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
160                tomk -= uma_size;
161
162                /* For reserving UMA memory in the memory map */
163                uma_memory_base = tomk * 1024ULL;
164                uma_memory_size = uma_size * 1024ULL;
165        }
166
167        /* The following needs to be 2 lines, otherwise the second
168         * number is always 0
169         */
170        printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
171        printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
172
173        /* Report the memory regions */
174        ram_resource(dev, 3, 0, 640);
175        ram_resource(dev, 4, 768, (tomk - 768));
176        if (tomk > 4 * 1024 * 1024) {
177                ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
178        }
179
180        add_fixed_resources(dev, 6);
181
182        assign_resources(dev->link_list);
183
184#if CONFIG_WRITE_HIGH_TABLES==1
185        /* Leave some space for ACPI, PIRQ and MP tables */
186        high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
187        high_tables_size = HIGH_TABLES_SIZE * 1024;
188#endif
189}
190
191        /* TODO We could determine how many PCIe busses we need in
192         * the bar. For now that number is hardcoded to a max of 64.
193         * See e7525/northbridge.c for an example.
194         */
195static struct device_operations pci_domain_ops = {
196        .read_resources   = pci_domain_read_resources,
197        .set_resources    = pci_domain_set_resources,
198        .enable_resources = NULL,
199        .init             = NULL,
200        .scan_bus         = pci_domain_scan_bus,
201#if CONFIG_MMCONF_SUPPORT_DEFAULT
202        .ops_pci_bus      = &pci_ops_mmconf,
203#else
204        .ops_pci_bus      = &pci_cf8_conf1,
205#endif
206};
207
208static void mc_read_resources(device_t dev)
209{
210        struct resource *resource;
211
212        pci_dev_read_resources(dev);
213
214        /* So, this is one of the big mysteries in the coreboot resource
215         * allocator. This resource should make sure that the address space
216         * of the PCIe memory mapped config space bar. But it does not.
217         */
218
219        /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
220        resource = new_resource(dev, 0xcf);
221        resource->base = DEFAULT_PCIEXBAR;
222        resource->size = 64 * 1024 * 1024;      /* 64MB hard coded PCIe config space */
223        resource->flags =
224            IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
225            IORESOURCE_ASSIGNED;
226        printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
227                     (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
228}
229
230static void mc_set_resources(device_t dev)
231{
232        struct resource *resource;
233
234        /* Report the PCIe BAR */
235        resource = find_resource(dev, 0xcf);
236        if (resource) {
237                report_resource_stored(dev, resource, "<mmconfig>");
238        }
239
240        /* And call the normal set_resources */
241        pci_dev_set_resources(dev);
242}
243
244static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
245{
246        if (!vendor || !device) {
247                pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
248                                pci_read_config32(dev, PCI_VENDOR_ID));
249        } else {
250                pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
251                                ((device & 0xffff) << 16) | (vendor & 0xffff));
252        }
253}
254
255#if CONFIG_HAVE_ACPI_RESUME
256extern u8 acpi_slp_type;
257
258static void northbridge_init(struct device *dev)
259{
260        switch (pci_read_config32(dev, SKPAD)) {
261        case 0xcafebabe:
262                printk(BIOS_DEBUG, "Normal boot.\n");
263                acpi_slp_type=0;
264                break;
265        case 0xcafed00d:
266                printk(BIOS_DEBUG, "S3 Resume.\n");
267                acpi_slp_type=3;
268                break;
269        default:
270                printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
271                acpi_slp_type=0;
272                break;
273        }
274}
275#endif
276
277static struct pci_operations intel_pci_ops = {
278        .set_subsystem    = intel_set_subsystem,
279};
280
281static struct device_operations mc_ops = {
282        .read_resources   = mc_read_resources,
283        .set_resources    = mc_set_resources,
284        .enable_resources = pci_dev_enable_resources,
285#if CONFIG_HAVE_ACPI_RESUME
286        .init             = northbridge_init,
287#endif
288        .scan_bus         = 0,
289        .ops_pci          = &intel_pci_ops,
290};
291
292static const struct pci_driver mc_driver __pci_driver = {
293        .ops    = &mc_ops,
294        .vendor = PCI_VENDOR_ID_INTEL,
295        .device = 0x27a0,
296};
297
298static void cpu_bus_init(device_t dev)
299{
300        initialize_cpus(dev->link_list);
301}
302
303static void cpu_bus_noop(device_t dev)
304{
305}
306
307static struct device_operations cpu_bus_ops = {
308        .read_resources   = cpu_bus_noop,
309        .set_resources    = cpu_bus_noop,
310        .enable_resources = cpu_bus_noop,
311        .init             = cpu_bus_init,
312        .scan_bus         = 0,
313};
314
315static void enable_dev(device_t dev)
316{
317        /* Set the operations if it is a special bus type */
318        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
319                dev->ops = &pci_domain_ops;
320        } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
321                dev->ops = &cpu_bus_ops;
322        }
323}
324
325struct chip_operations northbridge_intel_i945_ops = {
326        CHIP_NAME("Intel i945 Northbridge")
327        .enable_dev = enable_dev,
328};
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