source: trunk/src/mainboard/asus/m2v-mx_se/romstage.c

Last change on this file was 6531, checked in by stepan, 4 years ago

run uart_init() from console_init, just like the other console initialization functions.

Signed-off-by: Stefan Reinauer <stefan.reinauer@…>
Acked-by: Stefan Reinauer <stefan.reinauer@…>

File size: 5.5 KB
Line 
1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2006 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2006 MSI
7 * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
8 * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
23 */
24
25unsigned int get_sbdn(unsigned bus);
26
27#if CONFIG_K8_REV_F_SUPPORT == 1
28#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
29#endif
30
31#include <stdint.h>
32#include <string.h>
33#include <device/pci_def.h>
34#include <arch/io.h>
35#include <device/pnp_def.h>
36#include <arch/romcc_io.h>
37#include <cpu/amd/mtrr.h>
38#include <cpu/x86/lapic.h>
39#include <pc80/mc146818rtc.h>
40#include <console/console.h>
41#include <cpu/amd/model_fxx_rev.h>
42#include "northbridge/amd/amdk8/raminit.h"
43#include "cpu/amd/model_fxx/apic_timer.c"
44#include "lib/delay.c"
45#include "northbridge/amd/amdk8/reset_test.c"
46#include "northbridge/amd/amdk8/debug.c"
47#include "superio/ite/it8712f/early_serial.c"
48#include "southbridge/via/vt8237r/early_smbus.c"
49#include "cpu/x86/mtrr/earlymtrr.c"
50#include "cpu/x86/bist.h"
51#include "northbridge/amd/amdk8/setup_resource_map.c"
52#include <spd.h>
53
54#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
55#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
56
57static void memreset(int controllers, const struct mem_controller *ctrl) { }
58static void activate_spd_rom(const struct mem_controller *ctrl) { }
59
60static inline int spd_read_byte(unsigned device, unsigned address)
61{
62        return smbus_read_byte(device, address);
63}
64
65#include "southbridge/via/k8t890/early_car.c"
66#include "northbridge/amd/amdk8/amdk8.h"
67#include "northbridge/amd/amdk8/incoherent_ht.c"
68#include "northbridge/amd/amdk8/coherent_ht.c"
69#include "northbridge/amd/amdk8/raminit_f.c"
70#include "lib/generic_sdram.c"
71#include "cpu/amd/dualcore/dualcore.c"
72#include "cpu/amd/car/post_cache_as_ram.c"
73#include "cpu/amd/model_fxx/init_cpus.c"
74
75#define SB_VFSMAF 0
76
77/* this function might fail on some K8 CPUs with errata #181 */
78static void ldtstop_sb(void)
79{
80        print_debug("toggle LDTSTP#\n");
81        u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
82        reg = reg ^ (1 << 0);
83        outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
84        reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
85        print_debug("done\n");
86}
87
88#include "cpu/amd/model_fxx/fidvid.c"
89#include "northbridge/amd/amdk8/resourcemap.c"
90
91void soft_reset(void)
92{
93        uint8_t tmp;
94
95        set_bios_reset();
96        print_debug("soft reset \n");
97
98        /* PCI reset */
99        tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
100        tmp |= 0x01;
101        /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
102        pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
103
104        while (1) {
105                /* daisy daisy ... */
106                hlt();
107        }
108}
109
110unsigned int get_sbdn(unsigned bus)
111{
112        device_t dev;
113
114        dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
115                                        PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
116        return (dev >> 15) & 0x1f;
117}
118
119void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
120{
121        static const uint16_t spd_addr[] = {
122                // Node 0
123                DIMM0, DIMM2, 0, 0,
124                DIMM1, DIMM3, 0, 0,
125                // Node 1
126                DIMM4, DIMM6, 0, 0,
127                DIMM5, DIMM7, 0, 0,
128        };
129        unsigned bsp_apicid = 0;
130        int needs_reset = 0;
131        struct sys_info *sysinfo =
132            (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
133
134        it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
135        it8712f_kill_watchdog();
136        it8712f_enable_3vsbsw();
137        console_init();
138        enable_rom_decode();
139
140        printk(BIOS_INFO, "now booting... \n");
141
142        if (bist == 0)
143                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
144
145        /* Halt if there was a built in self test failure. */
146        report_bist_failure(bist);
147        setup_default_resource_map();
148        setup_coherent_ht_domain();
149        wait_all_core0_started();
150
151        printk(BIOS_INFO, "now booting... All core 0 started\n");
152
153#if CONFIG_LOGICAL_CPUS==1
154        /* It is said that we should start core1 after all core0 launched. */
155        start_other_cores();
156        wait_all_other_cores_started(bsp_apicid);
157#endif
158        init_timer();
159        ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
160
161        needs_reset = optimize_link_coherent_ht();
162        print_debug_hex8(needs_reset);
163        needs_reset |= optimize_link_incoherent_ht(sysinfo);
164        print_debug_hex8(needs_reset);
165        needs_reset |= k8t890_early_setup_ht();
166        print_debug_hex8(needs_reset);
167
168        vt8237_early_network_init(NULL);
169        vt8237_early_spi_init();
170
171        if (needs_reset) {
172                printk(BIOS_DEBUG, "ht reset -\n");
173                soft_reset();
174                printk(BIOS_DEBUG, "FAILED!\n");
175        }
176
177        /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
178        /* allow LDT STOP asserts */
179        vt8237_sb_enable_fid_vid();
180
181        enable_fid_change();
182        print_debug("after enable_fid_change\n");
183
184        init_fidvid_bsp(bsp_apicid);
185
186        /* Stop the APs so we can start them later in init. */
187        allow_all_aps_stop(bsp_apicid);
188
189        /* It's the time to set ctrl now. */
190        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
191        enable_smbus();
192        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
193        post_cache_as_ram();
194}
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