root/trunk/coreboot-v2/src/northbridge/amd/lx/northbridge.c

Revision 4394, 15.3 KB (checked in by myles, 2 days ago)

Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:

  1. Read Resources
  2. Avoid fixed resources (constrain limits)
  3. Allocate resources
  4. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources. All fixed resources will end up outside (above or below)
the allocated resources.

Domains usually start with base = 0 and limit = 2address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources. Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw@…>
Acked-by: Ronald G. Minnich <rminnich@…>
Acked-by: Patrick Georgi <patrick.georgi@…>

Line 
1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
19 */
20
21#include <console/console.h>
22#include <arch/io.h>
23#include <stdint.h>
24#include <device/device.h>
25#include <device/pci.h>
26#include <device/pci_ids.h>
27#include <stdlib.h>
28#include <string.h>
29#include <bitops.h>
30#include <cpu/cpu.h>
31#include <cpu/amd/lxdef.h>
32#include <cpu/x86/msr.h>
33#include <cpu/x86/cache.h>
34#include <cpu/amd/vr.h>
35#include <cpu/cpu.h>
36#include "chip.h"
37#include "northbridge.h"
38#include "../../../southbridge/amd/cs5536/cs5536.h"
39
40
41/* here is programming for the various MSRs.*/
42#define IM_QWAIT 0x100000
43
44#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */        /* in high */
45#define DMCF_SERIAL_LOAD_MISSES  (2)    /* enabled */
46
47/* these are the 8-bit attributes for controlling RCONF registers */
48#define CACHE_DISABLE (1<<0)
49#define WRITE_ALLOCATE (1<<1)
50#define WRITE_PROTECT (1<<2)
51#define WRITE_THROUGH (1<<3)
52#define WRITE_COMBINE (1<<4)
53#define WRITE_SERIALIZE (1<<5)
54
55/* ram has none of this stuff */
56#define RAM_PROPERTIES (0)
57#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
58#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
59#define MSR_WS_CD_DEFAULT (0x21212121)
60
61/* 1810-1817 give you 8 registers with which to program protection regions */
62/* the are region configuration range registers, or RRCF */
63/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
64/* so no left-shift needed for top or base */
65#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
66#define RRCF_LOW_CD(base)       RRCF_LOW(base, CACHE_DISABLE)
67
68/* build initializer for P2D MSR */
69#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
70#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
71#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
72#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
73#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
74#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
75#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
76
77extern void graphics_init(void);
78extern void cpubug(void);
79extern void chipsetinit(void);
80extern uint32_t get_systop(void);
81
82void northbridge_init_early(void);
83void setup_realmode_idt(void);
84void do_vsmbios(void);
85
86struct msr_defaults {
87        int msr_no;
88        msr_t msr;
89} msr_defaults[] = {
90        {
91                0x1700, {
92        .hi = 0,.lo = IM_QWAIT}}, {
93                0x1800, {
94        .hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo =
95                            DMCF_SERIAL_LOAD_MISSES}},
96            /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
97            /* for 180a, for now, we assume VSM will configure it */
98            /* 180b is left at reset value,a0000-bffff is non-cacheable */
99            /* 180c, c0000-dffff is set to write serialize and non-cachable */
100            /* oops, 180c will be set by cpu bug handling in cpubug.c */
101            //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
102            /* 180d is left at default, e0000-fffff is non-cached */
103            /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
104            /* we will not set 0x180f, the DMM,yet */
105            //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
106            //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
107            //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
108            //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
109            /* now for GLPCI routing */
110            /* GLIU0 */
111            P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),
112            P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
113            P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
114            /* GLIU1 */
115            P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
116            P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
117            P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), {
118        0}
119};
120
121/* Print the platform configuration - do before PCI init or it will not
122 * work right.
123 */
124void print_conf(void)
125{
126#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
127        int i;
128        unsigned long iol;
129        msr_t msr;
130
131        int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
132                CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
133                CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
134                GLCP_DELAY_CONTROLS, GL_END
135        };
136
137        int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
138                MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
139                GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
140                GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
141                MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
142                GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
143                GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
144                GLIU0_GLD_MSR_COH, GL_END
145        };
146
147        int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
148                MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
149                MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
150                MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
151                GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
152                GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
153                GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
154                GLIU1_GLD_MSR_COH, GL_END
155        };
156
157        int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
158                CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
159        };
160
161        int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
162                MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
163                MDD_IRQM_PRIM, GL_END
164        };
165
166        int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
167                GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
168                GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
169        };
170
171        int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
172                MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
173                MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
174        };
175
176        printk_debug("---------- CPU ------------\n");
177
178        for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
179                msr = rdmsr(cpu_msr_defs[i]);
180                printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
181                             cpu_msr_defs[i], msr.hi, msr.lo);
182        }
183
184        printk_debug("---------- GLIU 0 ------------\n");
185
186        for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
187                msr = rdmsr(gliu0_msr_defs[i]);
188                printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
189                             gliu0_msr_defs[i], msr.hi, msr.lo);
190        }
191
192        printk_debug("---------- GLIU 1 ------------\n");
193
194        for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
195                msr = rdmsr(gliu1_msr_defs[i]);
196                printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
197                             gliu1_msr_defs[i], msr.hi, msr.lo);
198        }
199
200        printk_debug("---------- RCONF ------------\n");
201
202        for (i = 0; rconf_msr[i] != GL_END; i++) {
203                msr = rdmsr(rconf_msr[i]);
204                printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
205                             msr.hi, msr.lo);
206        }
207
208        printk_debug("---------- VARIA ------------\n");
209        msr = rdmsr(0x51300010);
210        printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
211                     msr.lo);
212
213        msr = rdmsr(0x51400015);
214        printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
215                     msr.lo);
216
217        printk_debug("---------- DIVIL IRQ ------------\n");
218        msr = rdmsr(MDD_IRQM_YLOW);
219        printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
220                     msr.lo);
221        msr = rdmsr(MDD_IRQM_YHIGH);
222        printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
223                     msr.hi, msr.lo);
224        msr = rdmsr(MDD_IRQM_ZLOW);
225        printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
226                     msr.lo);
227        msr = rdmsr(MDD_IRQM_ZHIGH);
228        printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
229                     msr.hi, msr.lo);
230
231        printk_debug("---------- PCI ------------\n");
232
233        for (i = 0; pci_msr[i] != GL_END; i++) {
234                msr = rdmsr(pci_msr[i]);
235                printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
236                             msr.hi, msr.lo);
237        }
238
239        printk_debug("---------- LPC/UART DMA ------------\n");
240
241        for (i = 0; dma_msr[i] != GL_END; i++) {
242                msr = rdmsr(dma_msr[i]);
243                printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
244                             msr.hi, msr.lo);
245        }
246
247        printk_debug("---------- CS5536 ------------\n");
248
249        for (i = 0; cs5536_msr[i] != GL_END; i++) {
250                msr = rdmsr(cs5536_msr[i]);
251                printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
252                             msr.hi, msr.lo);
253        }
254
255        iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
256        printk_debug("IOR 0x%08X is now 0x%08X\n",
257                     GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
258        iol = inl(GPIOL_EVENTS_ENABLE);
259        printk_debug("IOR 0x%08X is now 0x%08X\n",
260                     GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
261        iol = inl(GPIOL_INPUT_INVERT_ENABLE);
262        printk_debug("IOR 0x%08X is now 0x%08X\n",
263                     GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
264        iol = inl(GPIO_MAPPER_X);
265        printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
266                     iol);
267#endif                          //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
268}
269
270/* todo: add a resource record. We don't do this here because this may be called when
271  * very little of the platform is actually working.
272  */
273int sizeram(void)
274{
275        msr_t msr;
276        int sizem = 0;
277        unsigned short dimm;
278
279        /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
280        msr = rdmsr(MC_CF07_DATA);
281        printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
282
283        /* dimm 0 */
284        dimm = msr.hi;
285        /* installed? */
286        if ((dimm & 7) != 7) {
287                sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
288        }
289
290        /* dimm 1 */
291        dimm = msr.hi >> 16;
292        /* installed? */
293        if ((dimm & 7) != 7) {
294                sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
295        }
296
297        printk_debug("sizeram: sizem 0x%xMB\n", sizem);
298        return sizem;
299}
300
301static void enable_shadow(device_t dev)
302{
303}
304
305static void northbridge_init(device_t dev)
306{
307        //msr_t msr;
308
309        printk_spew(">> Entering northbridge.c: %s\n", __func__);
310
311        enable_shadow(dev);
312        /*
313         * Swiss cheese
314         */
315        //msr = rdmsr(MSR_GLIU0_SHADOW);
316
317        //msr.hi |= 0x3;
318        //msr.lo |= 0x30000;
319
320        //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
321        //printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
322}
323
324void northbridge_set_resources(struct device *dev)
325{
326        struct resource *resource, *last;
327        unsigned link;
328        uint8_t line;
329
330        last = &dev->resource[dev->resources];
331
332        for (resource = &dev->resource[0]; resource < last; resource++) {
333
334                // andrei: do not change the base address, it will make the VSA virtual registers unusable
335                //pci_set_resource(dev, resource);
336                // FIXME: static allocation may conflict with dynamic mappings!
337        }
338
339        for (link = 0; link < dev->links; link++) {
340                struct bus *bus;
341                bus = &dev->link[link];
342                if (bus->children) {
343                        printk_debug
344                            ("my_dev_set_resources: assign_resources %d\n",
345                             bus);
346                        assign_resources(bus);
347                }
348        }
349
350        /* set a default latency timer */
351        pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
352
353        /* set a default secondary latency timer */
354        if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
355                pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
356        }
357
358        /* zero the irq settings */
359        line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
360        if (line) {
361                pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
362        }
363
364        /* set the cache line size, so far 64 bytes is good for everyone */
365        pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
366}
367
368static struct device_operations northbridge_operations = {
369        .read_resources = pci_dev_read_resources,
370        .set_resources = northbridge_set_resources,
371        .enable_resources = pci_dev_enable_resources,
372        .init = northbridge_init,
373        .enable = 0,
374        .ops_pci = 0,
375};
376
377static const struct pci_driver northbridge_driver __pci_driver = {
378        .ops = &northbridge_operations,
379        .vendor = PCI_VENDOR_ID_AMD,
380        .device = PCI_DEVICE_ID_AMD_LXBRIDGE,
381};
382
383static void ram_resource(device_t dev, unsigned long index,
384                         unsigned long basek, unsigned long sizek)
385{
386        struct resource *resource;
387
388        if (!sizek)
389                return;
390
391        resource = new_resource(dev, index);
392        resource->base = ((resource_t) basek) << 10;
393        resource->size = ((resource_t) sizek) << 10;
394        resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
395            IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
396}
397
398#if CONFIG_HAVE_HIGH_TABLES==1
399#define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
400extern uint64_t high_tables_base, high_tables_size;
401#endif
402
403static void pci_domain_set_resources(device_t dev)
404{
405        int idx;
406        u32 tomk;
407        device_t mc_dev;
408
409        printk_spew(">> Entering northbridge.c: %s\n", __func__);
410
411        mc_dev = dev->link[0].children;
412        if (mc_dev) {
413                tomk = get_systop() / 1024;
414                /* Report the memory regions */
415                idx = 10;
416                ram_resource(dev, idx++, 0, 640);
417                ram_resource(dev, idx++, 1024, tomk - 1024);    // Systop - 1 MB -> KB
418
419#if CONFIG_HAVE_HIGH_TABLES==1
420                /* Leave some space for ACPI, PIRQ and MP tables */
421                high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
422                high_tables_size = HIGH_TABLES_SIZE * 1024;
423#endif
424        }
425
426        assign_resources(&dev->link[0]);
427}
428
429static void pci_domain_enable(device_t dev)
430{
431
432        printk_spew(">> Entering northbridge.c: %s\n", __func__);
433
434        // do this here for now -- this chip really breaks our device model
435        northbridge_init_early();
436        cpubug();
437        chipsetinit();
438
439        setup_realmode_idt();
440
441        printk_debug("Before VSA:\n");
442        // print_conf();
443
444        do_vsmbios();           // do the magic stuff here, so prepare your tambourine ;)
445
446        printk_debug("After VSA:\n");
447        // print_conf();
448
449        graphics_init();
450        pci_set_method(dev);
451}
452
453static struct device_operations pci_domain_ops = {
454        .read_resources = pci_domain_read_resources,
455        .set_resources = pci_domain_set_resources,
456        .enable_resources = enable_childrens_resources,
457        .scan_bus = pci_domain_scan_bus,
458        .enable = pci_domain_enable,
459};
460
461static void cpu_bus_init(device_t dev)
462{
463        printk_spew(">> Entering northbridge.c: %s\n", __func__);
464
465        initialize_cpus(&dev->link[0]);
466}
467
468static void cpu_bus_noop(device_t dev)
469{
470}
471
472static struct device_operations cpu_bus_ops = {
473        .read_resources = cpu_bus_noop,
474        .set_resources = cpu_bus_noop,
475        .enable_resources = cpu_bus_noop,
476        .init = cpu_bus_init,
477        .scan_bus = 0,
478};
479
480static void enable_dev(struct device *dev)
481{
482        printk_spew(">> Entering northbridge.c: %s with path %d\n",
483                    __func__, dev->path.type);
484
485        /* Set the operations if it is a special bus type */
486        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN)
487                dev->ops = &pci_domain_ops;
488        else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER)
489                dev->ops = &cpu_bus_ops;
490}
491
492struct chip_operations northbridge_amd_lx_ops = {
493        CHIP_NAME("AMD LX Northbridge")
494            .enable_dev = enable_dev,
495};
Note: See TracBrowser for help on using the browser.