| 1 | ## |
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| 2 | ## Compute the location and size of where this firmware image |
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| 3 | ## (coreboot plus bootloader) will live in the boot rom chip. |
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| 4 | ## |
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| 5 | if USE_FALLBACK_IMAGE |
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| 6 | default ROM_SECTION_SIZE = FALLBACK_SIZE |
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| 7 | default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) |
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| 8 | else |
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| 9 | default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) |
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| 10 | default ROM_SECTION_OFFSET = 0 |
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| 11 | end |
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| 12 | |
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| 13 | ## |
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| 14 | ## Compute the start location and size size of |
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| 15 | ## The coreboot bootloader. |
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| 16 | ## |
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| 17 | |
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| 18 | default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) |
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| 19 | default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) |
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| 20 | |
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| 21 | ## |
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| 22 | ## Compute where this copy of coreboot will start in the boot rom |
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| 23 | ## |
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| 24 | default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) |
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| 25 | |
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| 26 | ## |
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| 27 | ## Compute a range of ROM that can cached to speed up coreboot, |
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| 28 | ## execution speed. |
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| 29 | ## |
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| 30 | ## XIP_ROM_SIZE must be a power of 2. |
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| 31 | ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE |
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| 32 | ## |
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| 33 | default XIP_ROM_SIZE=65536 |
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| 34 | default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) |
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| 35 | |
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| 36 | |
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| 37 | ## |
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| 38 | ## Set all of the defaults for an x86 architecture |
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| 39 | ## |
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| 40 | |
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| 41 | arch i386 end |
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| 42 | |
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| 43 | ## |
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| 44 | ## Build the objects we have code for in this directory. |
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| 45 | ## |
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| 46 | |
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| 47 | driver mainboard.o |
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| 48 | |
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| 49 | if HAVE_PIRQ_TABLE |
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| 50 | object irq_tables.o |
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| 51 | end |
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| 52 | |
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| 53 | if USE_DCACHE_RAM |
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| 54 | #compile cache_as_ram.c to auto.inc |
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| 55 | makerule ./cache_as_ram_auto.inc |
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| 56 | depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" |
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| 57 | action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@" |
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| 58 | action "perl -e 's/\.rodata/.rom.data/g' -pi $@" |
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| 59 | action "perl -e 's/\.text/.section .rom.text/g' -pi $@" |
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| 60 | end |
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| 61 | end |
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| 62 | |
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| 63 | |
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| 64 | ## |
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| 65 | ## Build our 16 bit and 32 bit coreboot entry code |
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| 66 | ## |
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| 67 | mainboardinit cpu/x86/16bit/entry16.inc |
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| 68 | mainboardinit cpu/x86/32bit/entry32.inc |
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| 69 | ldscript /cpu/x86/16bit/entry16.lds |
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| 70 | ldscript /cpu/x86/32bit/entry32.lds |
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| 71 | |
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| 72 | ## |
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| 73 | ## Build our reset vector (This is where coreboot is entered) |
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| 74 | ## |
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| 75 | if USE_FALLBACK_IMAGE |
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| 76 | mainboardinit cpu/x86/16bit/reset16.inc |
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| 77 | ldscript /cpu/x86/16bit/reset16.lds |
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| 78 | else |
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| 79 | mainboardinit cpu/x86/32bit/reset32.inc |
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| 80 | ldscript /cpu/x86/32bit/reset32.lds |
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| 81 | end |
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| 82 | |
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| 83 | ### Should this be in the northbridge code? |
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| 84 | #not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc |
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| 85 | |
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| 86 | ## |
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| 87 | ## Include an id string (For safe flashing) |
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| 88 | ## |
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| 89 | mainboardinit arch/i386/lib/id.inc |
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| 90 | ldscript /arch/i386/lib/id.lds |
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| 91 | |
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| 92 | ### |
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| 93 | ### This is the early phase of coreboot startup |
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| 94 | ### Things are delicate and we test to see if we should |
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| 95 | ### failover to another image. |
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| 96 | ### |
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| 97 | if USE_FALLBACK_IMAGE |
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| 98 | ldscript /arch/i386/lib/failover.lds |
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| 99 | # mainboardinit ./failover.inc |
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| 100 | end |
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| 101 | |
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| 102 | ### |
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| 103 | ### O.k. We aren't just an intermediary anymore! |
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| 104 | ### |
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| 105 | |
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| 106 | ## |
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| 107 | ## Setup RAM |
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| 108 | ## |
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| 109 | mainboardinit cpu/x86/fpu/enable_fpu.inc |
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| 110 | |
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| 111 | if USE_DCACHE_RAM |
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| 112 | mainboardinit cpu/amd/model_lx/cache_as_ram.inc |
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| 113 | mainboardinit ./cache_as_ram_auto.inc |
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| 114 | end |
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| 115 | |
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| 116 | ## |
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| 117 | ## Include the secondary Configuration files |
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| 118 | ## |
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| 119 | dir /pc80 |
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| 120 | config chip.h |
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| 121 | |
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| 122 | chip northbridge/amd/lx |
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| 123 | device pci_domain 0 on |
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| 124 | device pci 1.0 on end # Northbridge |
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| 125 | device pci 1.1 on end # Graphics |
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| 126 | chip southbridge/amd/cs5536 |
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| 127 | # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK |
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| 128 | # SIRQ Mode = Active(Quiet) mode. Save power.... |
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| 129 | # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK |
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| 130 | register "lpc_serirq_enable" = "0x0000105a" |
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| 131 | register "lpc_serirq_polarity" = "0x0000EFA5" |
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| 132 | register "lpc_serirq_mode" = "1" |
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| 133 | register "enable_gpio_int_route" = "0x0D0C0700" |
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| 134 | register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash |
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| 135 | register "enable_USBP4_device" = "1" # 0: host, 1:device |
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| 136 | register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) |
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| 137 | register "com1_enable" = "0" |
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| 138 | register "com1_address" = "0x3F8" |
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| 139 | register "com1_irq" = "4" |
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| 140 | register "com2_enable" = "0" |
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| 141 | register "com2_address" = "0x2F8" |
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| 142 | register "com2_irq" = "3" |
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| 143 | register "unwanted_vpci[0]" = "0" # End of list has a zero |
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| 144 | device pci d.0 on end # Ethernet |
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| 145 | device pci e.0 on end # Slot1 |
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| 146 | device pci f.0 on # ISA Bridge |
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| 147 | chip superio/winbond/w83627hf |
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| 148 | device pnp 2e.0 off # Floppy |
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| 149 | io 0x60 = 0x3f0 |
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| 150 | irq 0x70 = 6 |
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| 151 | drq 0x74 = 2 |
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| 152 | end |
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| 153 | device pnp 2e.1 off # Parallel port |
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| 154 | io 0x60 = 0x378 |
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| 155 | irq 0x70 = 7 |
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| 156 | end |
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| 157 | device pnp 2e.2 on # Com1 |
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| 158 | io 0x60 = 0x3f8 |
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| 159 | irq 0x70 = 4 |
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| 160 | end |
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| 161 | device pnp 2e.3 off end # Com2 |
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| 162 | device pnp 2e.5 on # Keyboard |
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| 163 | io 0x60 = 0x60 |
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| 164 | io 0x62 = 0x64 |
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| 165 | irq 0x70 = 1 |
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| 166 | irq 0x72 = 12 |
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| 167 | end |
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| 168 | device pnp 2e.6 off end # CIR |
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| 169 | device pnp 2e.7 off end # GAME_MIDI_GIPO1 |
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| 170 | device pnp 2e.8 off end # GPIO2 |
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| 171 | device pnp 2e.9 off end # GPIO3 |
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| 172 | device pnp 2e.a off end # ACPI |
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| 173 | device pnp 2e.b off end # HW Monitor |
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| 174 | end |
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| 175 | end |
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| 176 | device pci f.2 on end # IDE Controller |
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| 177 | device pci f.3 on end # Audio |
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| 178 | device pci f.4 on end # OHCI |
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| 179 | device pci f.5 on end # EHCI |
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| 180 | end |
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| 181 | end |
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| 182 | # APIC cluster is late CPU init. |
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| 183 | device apic_cluster 0 on |
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| 184 | chip cpu/amd/model_lx |
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| 185 | device apic 0 on end |
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| 186 | end |
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| 187 | end |
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| 188 | end |
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