| 1 | - 2.0.0 |
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| 2 | - this NEWS file is neglected in favor of the svn commit logs. |
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| 3 | See http://tracker.coreboot.org/ |
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| 4 | - 1.1.8 |
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| 5 | - Store everything in arch |
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| 6 | - 1.1.7 |
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| 7 | - The configuration language has been cleaned up. No more link keyword. |
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| 8 | - Everything is now in the device tree. |
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| 9 | - The static and dynamic device trees have been unified |
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| 10 | - Support for setting the pci subsystem vendor and pci subsystem device has been added. |
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| 11 | - 64bit resource support |
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| 12 | - Generic smbus support |
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| 13 | - 1.1.6 |
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| 14 | - pnp/superio devices are now handled cleanly with very little code |
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| 15 | - Initial support for finding x86 BIST errors |
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| 16 | - static resource assignments can now be specified in Config.lb |
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| 17 | - special VGA I/O decode now should work |
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| 18 | - added generic PCI error reporting enables |
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| 19 | - build_opt_tbl now generates a header that allows cmos settings to |
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| 20 | be read from romcc compiled code. |
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| 21 | - split IORESOURCE_SET into IORESOURCE_ASSIGNED and IORESOURCE_STORED |
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| 22 | - romcc now gracesfully handles function pointers instead of dying mysteriously |
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| 23 | - First regression test in amdk8/raminit_test |
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| 24 | - 1.1.5 |
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| 25 | - O2, enums, and switch statements work in romcc |
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| 26 | - Support for compiling romcc on non x86 platforms |
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| 27 | - new romc options -msse and -mmmx for specifying extra registers to use |
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| 28 | - Bug fixes to device the device disable/enable framework and an amd8111 implementation |
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| 29 | - Move the link specification to the chip specification instead of the path |
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| 30 | - Allow specifying devices with internal bridges. |
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| 31 | - Initial via epia support |
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| 32 | - Opteron errata fixes |
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| 33 | - 1.1.4 |
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| 34 | Major restructuring of hypertransport handling. |
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| 35 | Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically |
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| 36 | Updates to hard_reset handling when resetting because of the need to change hypertransport link |
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| 37 | speeds and widths. |
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| 38 | (a) No longer assume the boot is good just because we get to a hard reset point. |
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| 39 | (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the |
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| 40 | boot counter. |
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| 41 | Updates to arima/hdama mptable so it tracks the new bus numbers |
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| 42 | - 1.1.3 |
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| 43 | Major update of the dyanmic device tree to so it can handle |
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| 44 | * subtractive resources |
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| 45 | * merging with the static device tree |
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| 46 | * more device types than just pci |
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| 47 | - 1.1.2 |
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| 48 | Add back in the hard_reset method from freebios1 this allows generic |
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| 49 | code to reset the box. |
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| 50 | Update the hypertransport setup code to automatically optimize |
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| 51 | hypertransport link widths and frequencies, and to call hard_reset |
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| 52 | if necessary for the changes to go into effect. |
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| 53 | - 1.1.1 |
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| 54 | Updates to the new configuration system so it works more reliably |
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| 55 | Removed a bunch of unused configuration variables |
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| 56 | Removed a bunch of unused assembly code |
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| 57 | - 1.1.0 |
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| 58 | A whole bunch of random ppc and opteron work we never put a good label on |
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| 59 | - 1.1.0 |
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| 60 | Intial development release of LinuxBIOS. |
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| 61 | Everything is thrown overboard and will be reincluded as necessary so we can |
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| 62 | get rid of the legacy baggage. Since LinuxBIOS was started we have developed |
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| 63 | some better techniques for some things, but we still hang on to the old ways |
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| 64 | because some ports that we want not to break depend on them. So we preserve |
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| 65 | them by preserve the 1.0.x series and keeping only the best practices for |
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| 66 | the 1.1.x series. When there is a stable port this code base will |
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| 67 | become LinuxBIOS 2.0.x and the core will become frozen. |
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